News Article

Million-dollar Mask Sets Change The World

Mask making is not an easy business these days. Semico Research describes some findings from its report "Mask Making: Rising Costs, Changing Business Models, New Technologies"

Mask making - long considered one of the less important elements of wafer processing - has gained a substantial amount of industry attention of late as a result of mask sets priced at $1 million and greater. Starting in the late 1990s, the wavelength of light commonly used in lithography exceeded the size of the smallest features defined by lithography - and the sub-wavelength era was born. The burden of printing 130nm and leading edge 90nm features has largely shifted to lowering the k1 factor in the Rayleigh equation (Figure 1) of optical resolution that covers variables that do not relate to the wavelength of the light or the numerical aperture of the lens. The quality of the mask itself is one of the key contributors to k1. To meet this need for a low k1, mask makers are facing lower yields (masks that don't make it through the writing process), increased mask complexity with the use of resolution enhancement techniques (RET) and much higher cost of ownership (COO) for the mask making tools.

Fig.1: Rayleigh equation for optical resolution

In fact, industry-wide "sticker shock" over mask prices has caused a lot of "buzz" and questions about mask making. Are mask sets really priced at $1 million or does this reflect initial pricing before mask makers' yields improve? If mask sets are that expensive now, what will they cost at the 65nm process node? Given expensive masks, how will the industry be able to produce application specific integrated circuits (ASICs) and prototypes economically? What alternatives to conventional masks and advancements in lithography that could mitigate mask cost are on the horizon? Research for a recent report on mask making from Semico Research has answered these questions and has revealed interesting insights regarding the changing landscape of mask making.

If integrated device manufacturers (IDMs) are set back by mask set prices at the 90nm process node, they will indeed be shocked by mask set prices at the 65nm node. A consensus opinion of mask set prices by process node gathered from industry experts is shown in Figure 2. Note that the graph depicts "typical" mask set prices (28-30 layer devices with 2-3 critical layers) for both initial operation and production (i.e. after yields have improved). Production prices are further delineated into minimum and maximum to describe a range of opinion.

Fig.2: Estimated mask set costs by node

This consensus opinion puts production mask set prices (after initial yields have improved) at between $0.8 million and $1.2 million at the 90nm node and between $1.3 million and 2.0 million at the 65nm node. Though this alone may be cause for alarm, consider what this means for low-volume ASICs, prototypes and other device types. By simply dividing the projected mask set prices at the 90nm and 65nm nodes by a range of wafer volumes, mask set cost per wafer may be derived (Figure 3).

Fig.3: Projected mask set cost per wafer

Small volume dilemma

Obviously, developers of ASICs and prototypes face a dilemma: How can they deliver devices at a reasonable price when mask cost alone ranges from $8000 to $20,000 per wafer at a production level of 100 wafers? In fact, many ASIC devices and all prototypes require fewer than 100 wafers and mask set cost per wafer increases proportionately. Note also that mask set cost does not materially increase wafer cost when a few thousand wafers are produced by the mask set as is the case for high-volume device types such as microprocessors (MPUs) and dynamic random access memory (DRAMs).

With resounding unanimity, ASIC manufacturers and other industry experts insist that demand for ASICs, custom system on chips (SOCs) and similar device types remains strong. To meet this demand, manufacturers are increasingly abandoning expensive masks in favour of a number of current and future alternative manufacturing techniques that share high mask set costs or avoid them altogether. These techniques include:

* Direct write tools that scan and modulate an electron-beam (e-beam) to directly expose resist on a wafer in a pattern without a mask - thus, this technology is also known as "maskless lithography". One such direct write tool is projected to be introduced in 2004 by the recently announced joint venture between the Netherlands' ASML and Sweden's Micronic Laser Systems.

* Multi-project wafer (MPW) designs where one mask set is used to develop as many as six prototypes or perhaps variations of one prototype thus commensurately sharing mask set cost.

* Multi-layer designs that employ individual masks that contain 4-6 layers of one device per mask thus proportionately reducing mask cost.

* "Shuttle services" such as TSMC's "CyberShuttle" that permit ASICs or prototypes from several companies to be processed at one time using one mask set thus splitting the mask cost by the number of designs.

* An ASIC design technique, dubbed "structured array", which features pre-verified cores that are typically placed in functional blocks that need only two or three metal layers (and hence only two or three new masks) to wire them together. Both LSI Logic and NEC have recently announced such "structured array" offerings.

While the reduced cost benefit of these techniques comes at a cost of lower stepper throughput or die production rate, the techniques offer an excellent tradeoff for ASIC or prototype development since relatively few devices are required to meet market or development needs.


Additionally, immersion lithography (IL) promises to relieve the pressure on mask makers by improving stepper resolution through increased numerical aperture (NA) in the resolution-defining Rayleigh equation (Figure 4). NA may be increased to about 1.2 (vs. a nominal 0.8 for most steppers today) because the usual exposure light transmission media, air, between the objective lens of the stepper and the wafer is replaced by ultra-pure deionised (DI) water (or some other transparent liquid such as Fomblin). This method of improving NA has been known and used in microscopy for more than 150 years but has only been applied in lithography for semiconductor processing recently as engineers in stepper companies have searched (perhaps even scratched about) for any means to improve resolution.

Fig.4: Numerical aperture for air (left) and immersion lithography right

Why does NA increase by replacing air with DI water? Simply speaking, NA increases because water permits more light to be refracted onto the wafer surface rather than reflected back into the lens at the lens-air interface (Figure 5). If n is increased from 1.0 (for air) to about 1.47 (for DI water), then NA increases proportionately for the same value of wavelength. In practice, tool suppliers have found that NA actually increases to about 1.2. Fomblin, a mixture of fluorinated polymers with n~1.3, has also been proposed as a transmission media by experimenters because it's chemically inert, non-flammable, and non-toxic.

Fig.5: Immersion allows light paths that would reflect back into the tool with a dry system, increasing NA

Recalling the Rayleigh equation, the resolution varies inversely to NA such that for resolution improvement for an NA increase from 0.8 to 1.2 is approximately 0.8/1.2=0.667 - resolved feature sizes will be about 1/3 tighter.

Experimentation at the Rochester Institute of Technology has demonstrated that NA in a 193nm stepper using IL actually increased 44%, which would translate to a resolution improvement of about 30% in the case of a stepper with an NA of 0.80.

All three major stepper manufacturers are reportedly developing IL technology, no doubt spurred by pressure from lithographers everywhere. This pressure can best be summarised in the words of one manufacturing vice-president, who said euphemistically that his company "is expressing a strong desire" that stepper manufacturers find a way to make IL work because the technology will extend the life of as stepper by at least one process node. With no technological "showstoppers" currently in sight, IL should be available in less than one year.


In addition to mask set prices, a compelling need to form alliances with IDMs is shaping the world of mask making. The job of mask makers has become much more difficult and expensive with the advent of sub-wavelength lithography. The days of starting a mask house with a few laser writers and wet etch tools are now a distant memory. As little as ten years ago, a "litho cell" for mask makers (consisting of a laser mask writer, a coat/develop track and inspection/repair tool) would cost less than $10 million. Today, 50keV e-beam mask writers alone cost $10-15 million and KLA's latest inspection tool is priced at $7.5-18 million. Mask blanks used to cost $500-700 for simple binary masks, but now blanks for some phase-shift mask (PSM) applications fetch $4000-5000. E-beam resists are priced at $1200-1500/gallon. Clearly, the price of being in the mask business has dramatically increased.

Furthermore, the market for masks is shrinking commensurate with the decreasing number of new chip designs and use of alternatives to conventional masks (as listed above). The constant march to more functionality on a chip drives one-chip solutions (e.g. one-chip cell phones and DVD players) while some functions are moving from chip-based hardware realisation to software solutions. Thus, new chip designs are more complex but their numbers are substantially fewer.

Consequently, merchant mask makers (MMMs) are facing a most difficult set of business conditions. Though the number of masks is decreasing and the cost of mask making is increasing, MMMs are not able to raise prices. As evidence of this, US-based MMMs have not been able to earn a return on their heavy capital and R&D investment in the past few years and their income statements show mounting losses. IDMs constantly call for better communication and partnerships with mask maskers, but they just as often "beat up" mask makers on price and turnaround time. Japanese MMMs do not report financial data that can be separated from a division of their parent companies, but they would likely show returns similar to their US counterparts if they did.

As a result, MMMs must form alliances with their customers (IDMs) to share capex and R&D costs in order to improve their financial condition (Figure 6). The Advanced Mask Technology Center (AMTC), an alliance between Dupont Photomask, AMD and Infineon in Dresden, Germany, offers an excellent example of how costs can be shared and mask technology advanced. Each partner owns an equal share of AMTC's mask output and the project has been bolstered by Û98 million in "investment aid" from the European Commission. Projected to produce masks for critical layers at the 130nm and 90nm process technology nodes, AMTC will cost the partners about Û360 million in the next five years. Notably, DNP (Dai Nippon Printing) has recently purchased the mask making operation of ST Microelectronics in Agrate, Italy. This will not only win DNP with another large customer, but also it will provide a production base for sale of masks throughout the European Union.

SUSS MicroTec And SET To Develop Equipment Solution For 3D Chip Integration
CEA-Leti Breakthrough For Next-Generation Memories And RRAM Energy-Storage
CEA-Leti Unveils Navigation-Grade Gyroscopes
YES Partners With Osiris For Edge Film Removal Technology
ALD Is Taking Off In More-than-Moore Applications
Are You Facing Decisions And Challenges With Interconnects, Pattern Transfer, 3D Scaling And Atomic Scale Processing And Integration?
BASF And Entegris Sign Agreement On Sale
Brewer Science Presents Best Practices For Workplace Culture At SEMICON West
The All-round Smart Proximity Sensor Chip
Mycronic Receives Order For An SLX Mask Writer
Park Systems Combines AFM With White Light Interferometry
ERS Electronic Appoints Mark Wachter As Chief Financial Officer
NTU Singapore Launches Quantum Science And Engineering Centre
ULVAC Expands Process Capability
SiLC Rolls Out Chip-Integrated FMCW LiDAR Sensor
3D-Micromac AG Appoints Hartmut Schubert To Chief Technology Officer
Detecting And Classifying Defects In Semiconductor Manufacturing Via Atomic Force Microscopy
Edwards Launches New Cryopump
ClassOne Appoints Industry Veteran Ken Gibbons
Kurt J. Lesker Acquires KDF Electronics & Vacuum Services
3D-Micromac AG Appoints Marko Gerlach Chief Financial Officer
Brewer Science’s Newly Launched Smart Devices Will Be Displayed At CES
Siemens Collaborates With PDF Solutions To Boost IC Yield And Speed Time
Imec Demonstrates Significant Performance Gains Utilizing Backside 3D SOC Interconnects

Search the news archive

To close this popup you can press escape or click the close icon.
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.

Please subscribe me to:


You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
Live Event