News Article

Porous CVD Ultra Low-k For 65nm And Beyond

Reducing k values of dielectrics below 2.5 presents major semiconductor process challenges. The need to introduce pores into low-k materials creates serious process weakness. Keith Buchanan of Trikon Technologies describes some of the factors involved and possible solutions for his company's Orion low-k dielectric.

Chemical vapour deposition (CVD) can be used to produce nano-porous, ultra low k (k<2.5) films to meet the requirements of sub-90nm technology interconnects. Process optimisation allows the tailoring of such film properties as carbon content and pore size distribution, and these in turn strongly influence the film's mechanical properties. The CVD ultra-low k films are well suited for use in advanced dual damascene interconnects using via-1st integration with timed etch for the trench.

Orion is a family of nano-porous, SiCOH-type low k dielectric films deposited using Trikon's Planar P300 cluster tool and chemical vapour deposition (CVD) process technology. Developed for use in 65nm and 45nm technology node interconnects, the k value is tuneable from 2.8 to as low as 1.9.

Generically, Orion is a nano-porous, hydrogenated silicon oxy-carbide. The overall dielectric constant of the as-deposited film is a function of the dielectric constant of the matrix material surrounding the pores, and of the volume porosity (kpores assumed to be 1.0). Incorporation of significant porosity is needed to produce films with k values less than 2.5.

However, the deposition process must also be tuned to maximise hardness and elastic modulus - these properties largely determine the resilience of the low k films to the mechanical stresses imposed by chemical mechanical planarisation (CMP) and packaging. Film hardness and elastic modulus are dependent on both the carbon content of the films and on the volume porosity and pore size distribution. Control of pore size distribution will also influence ease of integration through process steps such as wet cleans and metal barrier deposition. It is therefore necessary to carefully engineer the CVD process to optimise k along with the mechanical and electrical properties of the film.

Figure 1 shows Si-CH3 absorbance data comparing a 'high' carbon low k film with a 'low' carbon process. Although both processes produce films with dielectric constant 2.1-2.2, the films with less carbon are significantly harder. The interaction between k value, pore size range and hardness is demonstrated in Table 2, where hardness values are given for three Orion film variants. All three films were deposited using the same tool hardware and precursor gases and the hardness variation is achieved through process recipe tuning. Film hardness is seen to be a function of pore size range. Films with the smallest average pore size and smallest pore size distribution give the greater hardness values. By varying the CVD process conditions, film hardness can be varied by a factor of five with less than 10% variation in k value.

Film hardness vs. FTIR spectrum integrated methyl peak intensity, normalised
to Si-O


Via-first dual damascene is a favoured integration scheme due to its being relatively tolerant of via-trench misalignment. For 65nm interconnect technologies and beyond, use of a trench etch stop layer is not practicable because of the negative impact on effective k value. Avoidance of the trench etch stop layer also eliminates two interfaces from the dual damascene stack and this is potentially beneficial for mechanical and electrical reliability.

When the same low k material is used at both trench and via level, and in the absence of a trench etch stop layer, the development of a production-worthy timed trench etch process is challenging. It must be sufficiently controllable to give repeatable profiles across 300mm wafers. Also, the trench is stopped in the nano-porous low k dielectric and the etch process must be optimised to maintain a smooth etch-front. The optimised trench etch process used in dual damascene integration with SiC etch stop layer will not necessarily be useable when the etch stop layer is removed (Figure 2a). However, with process re-optimisation, excellent profiles can be obtained (Figure 2b).

Non-optimised (a) and optimised (b) timed trench etch profiles demonstrating
a smooth etch front in nano-porous Orion 2.2 low-k. Etch chemistry is

Compatibility with CVD metal barriers

Use of porous low k dielectrics makes integration of the metal diffusion barrier more challenging. To maintain acceptably low line effective resistivity in local interconnects, the barrier thickness must be 10nm or less, according to the International Technology Roadmap for Semiconductors (ITRS). Deposition of such thin layers into features etched in relatively dense (non-porous) low k dielectrics does not present a significant integration challenge. However, when porous low k dielectrics are used, the trench and via sidewalls of the porous low k dielectric must be 'sealed' so that the barrier cannot be penetrated by copper. Barrier penetration into porous low k dielectrics can be exacerbated by too large a pore size and also by the use of highly conformal CVD barrier deposition processes, especially atomic layer CVD.

Sidewall sealing can be accomplished by the deposition of a thin, conformal layer of dense dielectric. The required thickness will depend on pore size and the addition of a denser film will increase the effective dielectric constant between the metal lines. The inherent properties of the Orion 2.2 low k dielectric allow a different approach to pore sealing to be used. Studies show that trench sidewall sealing in Orion 2.2 can be achieved in-situ during etch/resist strip processing.

A magnified 'detail' image highlights the localised densified region on the trench sidewall (Figure 3). The densified layer is 5-8nm thick with the thickness dependent on the resist strip chemistry and processing conditions. The etch chemistry is CxFyHz and densification is achievable with a resist strip chemistry. Through-focus TEM imaging shows the densified layer to be non-porous while elemental analysis of the TEM foil by electron energy loss spectroscopy confirms that the densified trench sidewall is carbon-depleted and oxygen rich compared to the neighbouring porous low k material. Electron energy loss spectroscopy (EELS) data confirms that a MOCVD TiN(Si) copper diffusion barrier deposited over the densified trench sidewall does not diffuse into the porous low k dielectric (Figure 4).

Cross-sectional transmission electron microscope (XTEM) image of damascene
trench with Orion 2.2 porous low k and 8nm MOCVD TiN(Si) barrier

a) XTEM showing 8nm MOCVD TiN(Si) diffusion barrier in a damascene trench
etched into Orion 2.2. b) EELS Ti spectrum measured along axis A in (a).

1: Properties of an Orion 2.2 film targeted for 65nm technology

2: Film hardness as a function of pore size distribution and k value
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