Post-CMP Marangoni Drying Eliminates Defects
Next generation interconnects pose two new challenges for post-CMP cleaning: As device feature sizes shrink to 90nm and 65nm, defects as small as 0.1µm become yield killers. New extremely low-k dielectrics create another challenge - to dry these porous and hydrophobic films without leaving water marks. Because of these factors, the need arises to improve post-CMP drying capability beyond that provided by spin rinse dry.
Vapour drying technology is emerging for post-CMP cleaning applications in order to dry copper/low-k interconnect layers and to reduce yield-killing defects on 90nm and 65nm devices. A post-CMP cleaning process with integrated vapour drying eliminates water marks and reduces overall defects on copper/low-k patterned wafers, overcoming the limits of conventional spin rinse drying.
After cleaning, water removal from wafers is traditionally done by centrifugation followed by evaporation. To be effective, the technique demands uniform thinning of the water film, which is only possible if the wafers are hydrophilic. Low-k dielectrics are strongly hydrophobic, often with a contact angle greater than 50°. In the conventional spin rinse dryer, water films break apart into droplets on hydrophobic surfaces. As they evaporate, these drops precipitate material onto the wafer surface as defects (Figure 1). Because drying of hydrophobic surfaces is rapid and uncontrolled, spin rinse drying cannot avoid water-mark defects on low-k films. On patterned Cu/low-k wafers, energy dispersive x-ray (EDX) analysis of water marks shows that they contain copper (Figure 2). Water marks that bridge copper lines thus create a current leakage pathway that negatively impacts device reliability.
Addition of surfactants to the cleaning/rinsing process has extended the life of spin rinse dry technology to some low-k dielectrics, but provides only marginal solution to the water mark problem on the majority of low-k films, including the first generation low-k with k~3.0. Using hydrophilic capping layers on top of low-k to prevent exposure of the hydrophobic surface has seen a limited degree of success. With the addition of a cap, an additional interface is created for each metal layer in the interconnect stack and the adhesion at this interface is shown to be poor. In addition, cap layers have high relative k values (k>4.0), which elevates the effective k value for the entire stack and forces designers to use as thin a cap as possible. This in turn creates the possibility of partial cap removal from some structures/areas of the wafer, which brings the hydrophobic low-k surface in contact with the deionised water (DIW) once again.
The conventional spin-rinse-dry (SRD) process has three major steps: DIW rinse, spin dry and water film evaporation. DIW rinse removes any chemical residues carried over from prior modules, leaving a 10µm thick film of DIW on the wafer surface. Spin dry removes water from the substrate, making the water film thin enough for evaporation. With the current SRD configuration, the final remaining water film thickness that can be reached is about 0.2µm. The remaining water film is removed by convective and/or heat induced evaporation . Suspended particles less than 0.2µm remain on the wafer surface after the water has evaporated. As device feature sizes shrink to 90nm and 65nm, these particles are expected to become killer defects.
A new wafer drying technology needs to be integrated into the Cu/low-k CMP system, both to reduce the remaining water film thickness for less than 0.2µm suspended particle elimination and to reduce water marks on advanced dielectrics.
We designed the Desica vapour-dry module to replace the SRD in post-CMP cleaning. In the vapour-dry operation, a wafer enters the rinse tank and then emerges vertically. Tiny nozzles focus nitrogen and isopropanol (IPA) vapour onto the interface formed between the water and the substrate as the wafer emerges from water. The IPA assists in drying the wafer by the Marangoni effect  (Figure 3). IPA is readily absorbed at the tip of the meniscus, where it lowers surface tension. The resulting surface tension gradient pulls water away from the wafer as it is lifted out of the bath. The entire process requires less than 60 seconds.
The residual film thickness is about 0.02µm , so evaporation will precipitate only 0.02µm or smaller particles, a 10x improvement over SRD. Another advantage of the bath-type dryer is that it prevents water film breakdown, which is a cause of water marks. The use of a full immersion rinse tank from which to gradually pull the wafer out into the IPA is crucial to achieving a stable and repeatable meniscus for every kind of wafer surface used, independent of the surface contact angle or wiring structure design on the wafer. This ensures a much broader process window for a wide variety of low-k and also conventional oxide surfaces that can be processed through the dryer, as compared to systems that apply IPA vapour to a localised area on a spinning wafer. The latter have a diminishing process window for pattern wafers that consist of both hydrophobic (low-k) and hydrophilic (copper) materials.
Marangoni drying is the final step of a four-step cleaning process (Figure 4). The first module, a megasonics immersion tank, uses elevated temperature and a proprietary chemical to dissolve copper oxide and loosen organic residue. The second and third steps use brush scrubbing for particle removal.
Three major parameters control drying efficiency in our module: nitrogen flow, IPA concentration and wafer lift speed. A process window design of experiments (DOE) was conducted by cleaning copper/low-k patterned wafers and inspecting them on an optical patterned wafer defect inspection system (Figure 5). The results of this work were:
* Nitrogen flow should be enough to carry IPA to the meniscus without breaking the film
* IPA concentration was optimised for minimum consumption and high process speed
* A variable wafer lift speed process was the most robust
After optimisation, the best known method (BKM) for the integrated cleaner and dryer eliminated removable defects larger than 0.24µm on polished PVD copper wafers. Patterned wafers had consistent, low defect counts. All IPA dryer splits show few defects relative to SRD (Figure 6). The BKM process proved repeatable throughout a 1000 wafer run. Defects on oxide blanket wafers were consistently low during the marathon (Figure 7).
Figure 8 compares the time dependent dielectric breakdown (TDDB) of wafers processed with vapour dry versus wafers processed with spin dry. In the TDDB test, the wafer is heated to an elevated temperature and a high electric field is placed across minimum metal-pitch lines to drive the dielectric to failure. Longer failure life under these conditions indicates greater dielectric integrity. The wafers processed with vapour dry have five times longer TDDB lifetimes, indicating that water-mark-free wafers processed with vapour dry have superior dielectric integrity.
For normal copper low-k wafers no surfactant is required anywhere in the process to obtain water-mark-free wafers.
The integrated IPA process saves money by eliminating the need for secondary post-clean and batch IPA dry to get rid of water marks on copper/low-k interconnects. Isopropanol use during the marathon run was less than 0.5grams per wafer. Process time is less than 60 seconds, making the process attractive for cleaning after high throughput interlayer dielectric (ILD) CMP processes.
Fig.1: Water marks on SRD dark-field image of a low-k blanket wafer.
Fig.2: EDX, optical and SEM images of copper-rich water marks on low-k or (centre) Cu and low-k lines.
Fig.3: Marangoni flow is from region I (high IPA concentration, low surface tension) to region II (low IPA concentration, high surface tension).
Fig.4: Post-CMP cleaner.
Fig.5: IPA drying optimisation. Copper low-k MIT patterned wafers, drying only. Metrology is on a Compass 3x tool.
Fig.6: Drying split vs. defects for MIT patterned copper low-k wafers.
Fig.7: Oxide blanket wafer defects during marathon.
Fig.8: Normalised time dependent dielectric breakdown (TDDB).
Nathan Stein, Guy Shirazi, Jianshe Tang, Robert Jackson, Greg Viloria, Younes Achkire, Wei-Yung Hsu, Applied Materials.
The authors acknowledge important contributions from Konstantin Smekalin, Dan Marohl, Rashid Mavliev, Boris Fishkin, Peter Chou, Zhitao Cao, and Richard Duran.
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