News Article


The relentless reduction in the size of chip features is imposing ever-growing demands on metrology.

by Bede X-ray Metrology chairman Stuart McIntosh

The move towards 90nm nodes and below is creating many new dynamics in semiconductor manufacturing. Fab managers are looking at all stages of the semiconductor wafer process to ensure that their current manufacturing technologies are a match for the increasing requirements. Metrology is no exception.

While conventional metrology tools have historically met measurement and analysis requirements for applications with line widths down to 130nm, the trend towards nodes of 90nm, 65nm and ultimately 45nm is creating an entirely new level of inspection requirements.

Even X-ray fluorescence (XRF), which, along with optical and X-ray technologies, has been a staple of semiconductor metrology technologies, is unable to distinguish between different layers containing the same element and is limited to layer thickness measurements above 100Å. And so it is becoming unsuitable for measuring and analysing thin films.

For a moment, lets put all this talk of 90nm nodes in perspective. The scaling of semiconductor device dimensions has historically been driven by Moores Law (named after Intel cofounder Gordon Moore), which predicts that the number of transistors that can be packed onto a single chip will double every 18 months to two years.

In recent history, this has meant that the minimum feature size of one technology generation (or node) has been about 70% of the size of the previous technology generation. New technology nodes have been introduced about every two to three years.

Heres where it gets interesting. In the 2003 International Technology Roadmap for Semiconductors (ITRS), the three-year interval between technology nodes has been maintained, but the relative feature sizes appear to differ from the historical 70% shrink. Namely, theyre smaller. This has called into question every assumption about what is - and what is not - adequate metrology technology to assess the effectiveness of applied layers.

Certainly, line width is a market driver that determines the selection of a metrology system, as is film thickness, which, for 45nm line width devices, will mandate layers as thin as 1.6nm, well beyond the capabilities of any type of measurement tool other than X-ray, and in particular, X-ray Reflectivity (XRR).

While XRR provides the capability for addressing such thickness requirements, an important third market driver is addressed by high-resolution XRD (HRXRD), and that is the ability to achieve a full materials characterisation by examining the molecular and atomic structure of each layer.

Such an analysis is essential for detecting hidden anomalies, such as lattice mismatches and stacking faults, and preventing a wafer being accepted that has met dimensional tolerances for the individual layers but is otherwise defective.

In short, the needs of the industry are catching up to the limitations of conventional metrology systems and are creating new opportunities for high-resolution X-ray metrology.

Lets look at what the industry might require of metrology tools as it approaches 90nm and beyond.

High-speed tools
Metrology can easily become a bottleneck in leading edge manufacturing. The current trend is for larger factories because semiconductor companies are now constructing fabs for highvolume 300mm production.

Larger fabs require high-speed equipment. On average, a 30,000 wafer-per-month fab at full utilisation will ship about 45 wafers per hour.

Each of those wafers has more than 400 processing operations, including metrology. Thus, the fab must complete about 18,000 wafer processing operations per hour. This involves a total of about 250 to 750 measurements and inspections per hour, depending on the sampling plan.

In-situ integrated metrology has an additional speed challenge. The metrology operation must not be slower than the rest of the cluster tool. The goal is to make metrology as invisible to wafer cycle time as possible.

Cost-effective manufacturing
The cost of manufacturing semiconductor wafers increases with each technology generation, while at the same time the average selling price of devices falls. Thus, the semiconductor industry is constantly fighting a battle to lower costs at every point in the process.

Understanding manufacturing costs is the first step to increasing profits. The ability to effectively identify cost drivers and manage cost reductions is a competitive advantage for metrology suppliers.

Over the past ten years, cost of ownership has migrated from an evangelical topic at a select few firms to an integrated part of corporate cultures. The driving force that propelled cost of ownership (COO) into the limelight was the disadvantage US manufacturers faced during the 1980s in their cost of capital. COO has been proven successful and has since been adopted by most major manufacturers regardless of geographic location.

COO provides an objective analysis method for evaluating equipment purchases. First, it provides a clear estimate of the life-cycle cost. The analysis highlights details that might be overlooked, thus reducing decision risk. COO can also evaluate processing and design decisions. Finally, COO provides communication between suppliers and users. They are able to speak the same language, comparing similar data and costs using the same analysis methods. This is particularly true in metrology, as wafer manufacturers must continuously reduce the cost per measurement.

Integration with production equipment
Both standalone systems and integrated metrology systems are in use in leading-edge manufacturing. Standalone systems are most often used for characterisation of new materials, processes, designs and equipment. However, integrated metrology systems are the growing manufacturing requirement. Tighter tolerances and processing requirements for leading edge processes are introducing the need for adaptive process control into manufacturing.

While this can be done without integrated metrology, integrating metrology into process equipment limits the number of wafers at risk between the processing operation and the measurement process.

Since process and metrology are in series, process throughput depends on metrology methods. Further, since the process requires measurement, there is an impact of measurement on work in progress (WIP). WIP inventory between a process step and subsequent inspection is at risk if the process drifts. Several operating methods minimise that risk. Send ahead (or look-ahead) samples eliminate WIP risk, but reduce process throughput and utilisation. Integrated in-situ metrology minimises risk with very little impact on utilisation.

Metrology data management
The challenges of integrated metrology do not end when a metrology system is bolted into a processing tool. The data from the metrology must be integrated as well. The 2004 ITRS identifies this as a difficult challenge. "Standards for process controllers and data management must be agreed upon. Conversion of massive quantities of raw data to useful information [is required] for enhancing the yield of a semiconductor manufacturing process."

Equipment reliability
Since metrology is generally required before a wafer can be passed on to the next processing stage, metrology can become a bottleneck in wafer fabrication. However, wafer measurements are also required to certify that equipment is operating properly before being released for use on production wafers. Thus, metrology equipment reliability is at least as important as production equipment reliability.

Multiple generation upgrade capability
Designing metrology equipment to address more than one technology node (generation) may actually be easier to achieve than for some process equipment. The metrology physics do not change with technology nodes the way that device physics are starting to change. Thus, the same metrology equipment that is purchased for use at 90nm should be easily upgradeable to 65nm and 45nm. Modular designs of platform, chamber, control systems and data management interfaces will facilitate longer equipment life. This, in turn, will improve cost of ownership.

Where this leads us is to better metrology tools to support semiconductor manufacturing processes that are surpassing all known metrology technologies, save one - X-ray. The challenge for Bede X-ray Metrology and others is to stay one step ahead of the ITRS Roadmap, and that will keep us all very busy for some time to come.




AngelTech Live III: Watch the virtual event ON-DEMAND!

AngelTech Live III was broadcast live on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and features online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

The event covered the whole spectrum of key developments affecting the compound semiconductor industry. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. This was considered a roadmap for this device, along with technologies for boosting its output.

With 3 interactive sessions over 1 day AngelTech Live III proved to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.



Search the news archive

To close this popup you can press escape or click the close icon.
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.

Please subscribe me to:


You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
{taasPodcastNotification} Array
Live Event