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The future of parametric testing

Integrated circuit devices continue to shrink in size, increase in density, and improve in performance every year. Manufacturing and testing these devices while simultaneously maintaining and improving yield has become increasingly difficult. David Ridsdale spoke to Dr. Stewart Wilson, European System Sales Manager for Parametric Test Systems at Agilent about the growing need for parametric testing in the industry.


At 90 nanometers and below, the testing challenges have increased for semiconductor manufacturers who need to ramp up their production lines as quickly as possible. Time-to-yield is becoming a more critical factor for business success at 90 nm process technology and below. High volume parametric data is needed to shorten the cycle time required to ramp up a wafer fab to full production. Higher throughput is needed to gather and analyse data quickly enough to be practical for use in the yield ramp-up phase, for either back-end of line (BEOL) testing or during in-line test.

Parametric testing is becoming an essential tool for the yield ramp-up phase as it can allow users to test more structures in less time with greater throughput. This is vital as companies seek to decrease the time to market in an ever-competitive market while dealing with ever-complex structures.

A parametric test measures all device parameters to see if they meet the specified values. In the production of semiconductor devices, it has historically been the case that functional testing is done on all units while parametric testing is done on a small percentage of special test die as test samples. With a growing amount of data to deal with in a shorter time this is becoming increasingly impractical and the amount of historical data means that companies can make informed decisions from parametric testing at points when only functional testing was possible.


Agilent has provided parametric testing for the industry as a key sector of their business and seeks to offer one of the widest ranges of solutions and price-performance points available. As an example, the 4070 Series provides the DC and RF measurement capabilities needed to test the 65 nm process technologies of today, as well as future needs of complex nano fabrication. All members of the 4070 Series family have complete DC parametric test capabilities, including Flash memory cell testing, capacitance versus voltage (CV) measurement and ring oscillator evaluation. Additionally, it is possible to integrate all models into a SECS/GEM-compatible 300 mm automated factory environment. I spoke to Dr. Stewart Wilson recently about parametric testing and where Agilent felt it would go in the industry.

1. Parametric test looks at whether a device meets certain preset variables. How difficult is it to set up these variables for an engineer?
Depends on the software they use. Agilent has software that is called SPECS that allows engineers to set up parametric test parameters in a quicker fashion. The software is based on assumptions of standard tests that are typically run on a chip. The Agilent systems are modularly adaptive and the earlier tool software will function on current tools even though the programming language has changed.

2. Please provide an example of time to set up the variables and how this affects time to market for manufacturers.
Depends on the chip being tested. Chips manufactured at the 65 to 45nm level require additional tests such as Critical Dimensions (CD) and high frequency as gate leakage current is higher. As the process geometry shrinks there are more active components on a chip and therefore more testing is required. Despite the increases, manufacturers request up to four times more the amount of data but within the same time, as they do not want throughput to be impacted. There is a need to gather a geometrically increasing amount of data in a quicker time frame. With software assistance companies can set up test parameters based on historical information that has been stored and gathered over many years. Once established for a given test chip, companies download data and then cross reference to the preset parameters. The information is pooled out to determine yield parameters and optimisation.

3.Parametric test has traditionally been about DC measurements at final metal. How do you see this changing in the future?
Most companies once only did parametric testing as an end of the line test. With growing complexity companies are more likely to do parametric testing at first metal and each subsequent layer. This is due to the sheer complexity of manufacturing integrated circuits at the top end and to maximise yield feedback.


4. How do you think parametric test will evolve?
Even if companies hate to do it, RF measurements will become more vital as the technology becomes more pervasive. This is typically not a test that can be done functionally. Yield ramp up is also an area that will become more vital as companies will need to identify best manufacturing practices before devices reach full manufacturing capacity. Companies develop array structures that they can then test for defects. This is a long and tedious process. Agilent has a parametric array test option that reduces test time from days to hours.

5. Does there need to be links between DFM providers and test developers?
Although there are no formal links to DFM there is
a growing synergy between the two that will need to develop as device complexity increases. Yield improvement companies like HPL and PDF already make connections between the two groups when they look at yield ramps for manufacturers. These two companies use thier own proprietary test chip design to assist data feedback. The historical data that is collated and collected through testing feedback sets up future design for manufacturing. Without this historical data, designers would have no understanding of manufacturing parameters.

6. Parametric tests are generally performed on a small sample of tests as opposed to functional tests, will this continue to be the standard method of testing a large batch of chips?
My personal view is that parametric testing has to encompass more issues. Some testing parameters, such as gate leakage and via contacts, were historically considered second and third order effects in preference for manufacturers. These issues are now first order effects at the top end of manufacturing. As the amount of data increases the initial ramp up testing will be a greater sample size as more data will be required at this earlier stage. Functional testing will become extremely difficult at the billion transistor levels and I see parametric testing becoming more complimentary rather than additional. Parametric tests can provide enough data to ascertain functional status and decision making information. This will change over time and will depend on the specific company.

7. How does Agilent address yield enhancement and yield ramp up?
When developing a new chip the manufacturer will do a first run and obtain a poor yield. They will then run parametric testing over a period of at least six months to achieve yield viability and be able to do functional testing. This is a vast improvement of the 18 months it used to take to get a product ready. The decrease in time to market is a major driver for increasing yields at the earliest point to ensure profitability at the manufacturing stage. Companies can no longer afford mistakes moving towards manufacturability.

Agilent provides its array test option in the 4070 series of parametric testing. Due to the increase in complexity, IDM's will have to do wafer level testing during yield ramp. Testing at this point can take a long time with measurements like Vt, (threshold voltage), Idson, (drain source current on), Idsoff (drain source current off), memory cell capacitance, gate oxide brake down measurements, defectivity structure measurements, resistor measurements, etc. Using parametric testing at this point reduces the time by a significant factor. Agilent has recently partnered with a wafer systems partner to provide specialist software and hardware interfaces that will provide parallel WLR parametric testing, reducing time factors even further. Speeding the time to yield and then to market will be a key factor of success for manufacturers.

8. Do you feel there needs to be greater automation for parametric testing and if so at what point in the process should this be available to the engineer?
Yes. Most fabs would prefer to run with fewer individuals involved at the more complex chip levels. Although cost is a factor in this decision it is also due to defect control. At such precise parameters in manufacturing, the less people involved in the process, the less chance for accidental contamination. Increased automation allows companies to reduce human errors in manufacturing. Agilent's tool sets already have software interface compatible to current automation standards and can interface with newer systems, such as Linux based controls as many customers move towards open source systems. This is upwards compatible allowing existing tool owners to upgrade without having to completely purchase all new hardware and software.


9. How does Agilent address the need for higher automation?
Agilent has SPECS-FA (Semiconductor Process Evaluation Core Software - Factory Automation) within the parametric testers providing a ready to use interface. The software is a factory automation solution for parametric testers based on industry standard SPECS test shell. It offers flexible test control, multiple recipe management, dual ports, and supports CMS and SECS/GEM. It provides both a single and double wire connectivity solution depending on the manufacturer's needs.

10. What about WLR, (Wafer Level Reliability) and how does it refer to parametric testing?
Wafer Level Reliability is similar to device testing. At final metal the same measurements are made as at Yield Ramp but more measurements are made on areas such as electromigration and hot carrier injection. Many parameters change as they go through the processing loop and it is important to know the shift at each process stage.

At chip level a parametric tester could be used to make RF "S" parameter measurements like S12 (gain) and ft, (unity gain frequency). Other measurements could be things like "noise figure" etc. In addition a parametric tester can measure sub pA leakage currents, (not usually possible on a functional test system). Most other measurements at chip level would be made with a functional tester which might also measure some of the above measurements but with much reduced accuracy.

At Wafer Level the testing must be done quickly for the obvious time factor but also for the need to eliminate device heating problems. Pulse IV testing helps reduce heat issues especially at sub 65nm on Silicon On Insulator (SOI) manufacturing.

11. How do you see WLR developing for future?
End customers of devices, especially automobile manufacturers, will demand increasing data flow as they seek more information to improve the quality and reliability of their products. This information is vital for setting future relability. This increase in information will force more parallel testing in the future. Retrospective referencing Wafer Level Testing data to package part burn in data will improve future device realiability.

As manufacturing moves into nano fabrication, testing will have to adapt. Whatever issues are currently with us will be magnified at this level and there are many issues that have not even had the questions formulated, such as the definition of a ‘good' carbon nanotube. It is impossible to determine what this future will hold as history has taught us. The adoption of high k and low k materials is a primary example. High k was supposed to be the godsend to reduce switching issues but both have turned out to be difficult, as manufacturing at atomic levels has provided new and unforeseen challenges.

Any area where functional testing is perceived as difficult or an enormous amount of data is required will become growth areas for parametric testing.

Parametric testing will never replace functional testing but will become a greater complimentary companion as complexities increase.

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