Scaling CMOS Beyond FinFETs: From Nanosheets And Forksheets To CFETs
The FinFET transistor architecture is the workhorse of today’s semiconductor industry. But as scaling continues, undesired short-channel effects require the introduction of new transistor architectures. In this article, Julien Ryckaert, program director of 3D hybrid scaling at imec, sketches out an evolutionary path towards 2nm and beyond technology nodes. Part of these insights were presented at the 2019 IEEE International Electron Devices Meeting (IEDM).
The FinFET: today's leading-edge transistor
At every new technology generation, chipmakers have been able to scale transistor specs by 0.7x, delivering a 15% performance boost, a 50% area gain, a 40% power reduction as well as a 35% cost decrease at device level. Several years ago, the industry made the transition from ‘good old' planar MOSFET to FinFET transistor architectures in order to maintain this scaling path. In a FinFET, the channel between source and drain terminals is in the form of a fin. The gate wraps around this 3D channel, providing control from 3 sides of the channel. This multi-gate structure was designed to eliminate short-channel effects, which starts to degrade the transistor's performance at reduced gate lengths.
Superior short-channel control is crucial since it sets the foundations of device scaling - allowing shorter channel lengths and lower operating voltages.
The first commercial 22nm FinFETs were introduced in 2012. Since then, FinFET architectures have been improved for enhanced performance and reduced area. For example, the 3D nature of the FinFET allowed an increase in fin height to obtain a higher device drive current within the same footprint. Today, industry is ramping up production of 10nm/7nm chips with FinFETs ‘inside.' At the cell level of the most advanced nodes, standard cells with a track height of 6T (which is a measure of the cell area) feature down to 2 fins per device.
Natural evolution from FinFET to nanosheet