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ClassOne Simplifies Metallization While Improving On-Wafer Performance

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Reducing transistor size to increase performance has driven semiconductor manufacturing since Moore’s Law was first articulated. Only a handful of companies still pursue this; many others look to new device types and architectures that do not depend on shrinking transistors or increasingly complex and expensive equipment. ClassOne Technology is a leader in the anti-complexity revolution that champions high performance and cost-effective throughput. BY JOHN GHEKIERE, VICE PRESIDENT, PRODUCT AND TECHNOLOGY, AND CODY CARTER, PRODUCT ENGINEER, CLASSONE TECHNOLOGY

THE WITHERING MARCH of relentless device scaling described by Moore's Law has left a mere handful of device manufacturers in that race, with TSMC clearly in the technology lead. When the cost per transistor inflected to become more expensive with each generation, somewhere between 26 and 22 nm nodes, it drove even many of the larger and more powerful manufacturers to alternate paths of innovation and new means of bringing value; GlobalFoundries pivoted boldly into FD-SOI; STMicroelectronics into SiC. The broad expansion of new device types - in short, the ubiquitous adoption of microelectronic devices into almost every aspect of our daily lives - has brought about the More Than Moore era, where feature scaling is no longer the sole means of device innovation.

This sea change in device innovations has essentially occurred in the wake of feature scaling, in a space of free-mindedness around device architecture and the applicability of manufacturing steps defined by that ceaseless grind. The industry, in a sense, has been able to take a breath, and we now see clearly, perhaps surprisingly, that the pace of Moore drove into unit processes and capital equipment certain complexities that may add little or no value. Whereas More Moore brought an almost exponential increase in complexity to unit processes, More Than Moore, while retaining expectations around on-wafer performance, has kicked wide the door to reducing complexity.

The shift is not only timely; it is critically necessary in very practical ways. As the global race for semiconductor leadership continues to escalate, thousands of new semiconductor jobs are being opened with thousands more to come. It is an expansion not previously seen and its impact is the rapid dilution of experience in the workforce. Now, the complexities of setting up, operating and optimizing unit process equipment becomes a costly, and for many More Than Moore manufacturers, a debilitating challenge. Device manufacturers need the same performance from their equipment, but they need it to be simpler to use.

The truth of the impacts of Moore on complexity was made clear to me, in a previous role, during a visit to a major advanced memory manufacturer to discuss process equipment technology. I had traveled to share some recent development results, aiming to place equipment within a new R&D location within the fab. The senior technology director was pressing me on a particularly nuanced capability that our competitor had and we did not. Adding the capability meant introducing a complicated mechanical system submerged in a concentrated wet chemistry. From an engineering perspective, such a system was not only expensive, but it introduced a dozen new potential failure modes. I explained to him that we had studied that function and its effects in depth and could find no indication of any kind that it provided any benefit. I asked for clarity of its on-wafer benefit. He said, “John, you don't understand. If I can measure it, then you must control it.”

It became clear. The pace of Moore means that there is simply not sufficient time to investigate everything to complete understanding. Perception of risk is risk, thus, complexity is driven in, even if, in certain cases, that complexity serves as largely an insurance policy against factors that may or may not be important. Better to have the complexity (and cost) than the question.

The More Than Moore crowd are rising in the wake of Moore, where heightened complexity no longer offers assurances. It offers higher cost and more unwieldy process steps; and if it doesn't bring measurable benefit, then it simply isn't needed.


Figure 1: V-I plot comparing LCD of POR condition against modified condition

The opportunities are fruitful. This article will focus on the simplification of electrochemical deposition (we'll simply say plating), which when compared to the entirety of semiconductor unit processes, already lies somewhere in the middle in terms of complexity. Plating is also broadly and deeply captured by a great host of patents. As a basic technology, plating is already more than 200 years old; yet, as we will show, even its fundamentals are ripe for innovations that simplify operation while not only maintaining on-wafer performance, but improving it.

Plating remains an enabling, cost effective and highly-flexible option for metallization. The means of producing high quality plating and excellent on-wafer results are well established. The principles behind great performance are no longer the domain of one or two providers.

Uniform deposition by plating requires careful sculpting of two key factors: the electric field profile and the fluid motion profile.

As it turns out, the electric field is actually the easier of the two to perfect. Computational Fluid Dynamic modeling (CFD) provides an exceptionally accurate and predictive model around the electric field and its ultimate effects on on-wafer performance, namely film deposition rate. The need here is to deliver a zero-gradient potential at the wafer surface. The electric field wants to be zero-gradient so this aspect of reactor engineering has a lot to do with developing hardware that “stays out of the way.”
In terms of the actual state of reactor hardware in the industry, however, the scaling race resulted in over-engineering of plating chambers for most More Than Moore applications and, arguably, many applications at >32nm node.