+44 (0)24 7671 8970
More publications     •     Advertise with us     •     Contact us
 
Loading...
News Article

Cadence Design IP portfolio in TSMC’s N5 Process Gains Broad Adoption

News

Cadence Design Systems has announced a wide range of leading semiconductor and system customers have successfully adopted the comprehensive line-up of Cadence® Design IP in TSMC’s industry-leading 5nm process technology. Designed to the latest state-of-the-art interface standards, the Cadence’s Design IP portfolio enables customers to develop the most advanced SoCs for the most demanding applications, including high-performance computing (HPC), artificial intelligence/machine learning (AI/ML), networking, storage, and automotive. The IP portfolio from Cadence in TSMC’s N5 process includes 112/56/25/10 Gbps Ethernet PHY/MAC, PCIe 6.0/5.0/4.0/3.1 PHY/Controller, 40Gbps UltralinkTM D2D PHY, and complete PHY/Controller for GDDR6, DDR5/4, and LPDDR5/4x.

Cadence’s design IP in TSMC’s N5 process delivers optimal power, performance and area (PPA) with rich feature sets to enable uncompromised differentiation, versatility and innovation for large-scale SoC designs. In addition, Cadence provides full subsystem deliveries with integrated PHY and controller IP to simplify integration, minimize risks, and enable faster time to market.

“TSMC worked closely with Cadence, our long-standing ecosystem partner, to enable leading-edge designs, which deliver significant power, performance and area improvements on our advanced technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “The strong collaboration between Cadence’s Design IP and TSMC’s IP9000 teams promotes high-quality IP delivery to help our mutual customers achieve first-pass silicon success and faster time-to-market.

"Cadence has collaborated with TSMC for decades to provide high-quality silicon-proven IP on advanced process nodes to meet the most demanding requirements for HPC, AI/ML, networking, storage, and automotive applications;” said Rishi Chugh, vice president of Design IP Product Management at Cadence. "The wide adoption of our Design IP in TSMC’s N5 process demonstrates the excellence and quality of Cadence’s Design IP, which is empowering customers to design highly differentiated product solutions.”

The N5 Design IP portfolio is part of the broader Cadence IP portfolio that supports the Cadence Intelligent System Design™ strategy. Through the continued development of our comprehensive Design IP portfolio, Cadence is enabling customers to achieve SoC design excellence at advanced nodes. For more information, please visit www.cadence.com/go/designipport.

SPEA donates test equipment to university in Thailand
SONOTEC and S3 Alliance join at SEMICON Europa
Luminaries like high-NA EUV and curvilinear photomasks
SensiML and Silicon Technology join forces
TRI launches high-performance 3D AXI
SONOTEC and S3 Alliance join at SEMICON Europa
Marquee Semiconductor expands Indian presence
Micron begins Memory Manufacturing Fab
SiLC Technologies advances Machine Vision
Renesas partners with EdgeCortix
Gradiant acquires H+E Group
Webinar: Hydrogen Generation Industry Innovations to Meet Expanding North American Fab Hydrogen Requirements
EdgeCortix set to disrupt the edge market?
Evonetix places first DNA Synthesis Development Platform at Imperial College London
ASE launches Integrated Design Ecosystem
Cohu acquires Equiptest Engineering
Advantest wins 2022 Best Supplier Award from ASE Holdings
SEMI welcomes new board members
Advanced Energy breaks ground on flagship factory
GlobalFoundries opens new Malaysia office
TSMC reveals 'breakthrough' set to redefine the future of 3D IC
Delphon announce new VP, strategic marketing & business development
Particle Measuring Systems Announces Acquisition of EMS
Ireland begins high-volume production of Intel 4 Technology
Advantest to showcase latest test solutions
200 gigabits per second
KemLab Inc. applauds CHIPS Act's commitment
200mm fabs to reach record capacity by 2026
Governor DeSantis dedicates $50 million for workforce development
DOD names eight 'Microelectronics Commons' Hubs
TSMC accelerates renewable energy adoption
Mouser signs global agreement with MediaTek
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: