Huawei outlines “τ Scaling” vision for the post-Moore semiconductor era

At ISCAS 2026, Huawei’s He Tingbo delivered one of the semiconductor industry’s most closely watched keynote speeches, presenting what she described as a new path for semiconductor evolution in the post-Moore era.

Framed around the concept of “τ Scaling,” the presentation outlined Huawei’s efforts over the past six years to continue improving chip performance despite the slowing of traditional geometric scaling and restrictions surrounding access to leading-edge lithography technologies.

The speech offered a detailed look at Huawei’s emerging semiconductor strategy, covering everything from smartphone processors and advanced packaging to AI systems, optical interconnects and future chip architectures. More significantly, it represented a broader philosophical shift away from conventional transistor scaling as the sole engine of progress.

Instead of relying primarily on shrinking geometries, Huawei argues that future semiconductor advances will increasingly depend on optimizing time-related characteristics across devices, circuits, chips and systems.

Beyond moore’s law
He began by acknowledging the historical importance of Moore’s Law in driving decades of computing progress.

For years, geometric scaling enabled the semiconductor industry to deliver faster processors, more capable smartphones and increasingly powerful computing systems at economically viable costs. However, the industry now faces mounting physical and economic challenges as transistor dimensions approach practical limits.

According to He, these challenges emerged even earlier for Huawei because of restrictions affecting access to advanced manufacturing technologies and lithography equipment.

“Geometric scaling plateaued for us six years ago,” she explained. “We started to rethink the nature of Moore’s Law and electronic systems.”

This led Huawei to focus on what it calls “time scaling,” or τ scaling, named after the time constant τ = RC that governs many electrical characteristics within semiconductor systems.

The company’s central argument is that semiconductor progress has never been purely about shrinking physical dimensions. Geometric scaling historically delivered benefits because it also improved timing characteristics — faster transistors, lower latency, shorter signal paths and higher operating frequencies.

Huawei’s proposal is therefore to shift optimization priorities away from purely geometric shrinkage and toward reducing delays throughout the electronic system stack.

Time as the new scaling metric
In practical terms, Huawei believes improvements can still be achieved across devices, circuits, chips and systems even without aggressive node shrinks.

At the device level, He explained that performance gains can still come from RC optimization techniques, including improvements to front-end and back-end processes. Technologies such as high-k metal gate structures and strained silicon were cited as examples already used successfully in previous Huawei products.

The broader idea is to optimize systems according to time-domain behavior rather than relying solely on transistor dimensions.

Huawei argues that this “τ-centric” methodology can apply across twelve orders of magnitude, ranging from picosecond-scale transistor switching to second-scale system-level operations.

At the circuit level, the company is targeting reductions in propagation delay through improved interconnect design, lower parasitic resistance and capacitance, shorter signal paths and optimized clock distribution.

At the system level, Huawei sees architecture and system optimization becoming increasingly important drivers of future performance gains.

The emergence of “LogicFolding”
The centerpiece of the presentation was Huawei’s introduction of a new methodology called “LogicFolding.”

According to He, LogicFolding represents a fundamentally new design methodology for digital systems based on vertically stacked active logic layers.

The concept involves distributing critical logic paths across multiple vertically integrated planes to shorten physical signal paths, reduce parasitic effects and improve timing performance.

Huawei claims this approach enables simultaneous optimization of power, performance, density and cost.

Traditional digital circuits rely heavily on managing timing relationships between sequential logic stages. Critical-path timing remains one of the dominant constraints limiting clock frequency and overall chip performance.

Huawei’s LogicFolding approach attempts to address this by physically compressing propagation distances between flip-flop stages.

By moving logic vertically rather than spreading it horizontally across increasingly large monolithic dies, Huawei says it can significantly reduce signal wiring lengths, improve clock integrity and lower timing margins.

The company argues that this allows chips to run faster while also improving efficiency.

Hybrid bonding and advanced packaging
Achieving LogicFolding required substantial advances in hybrid bonding and packaging technologies.

Huawei stated that successful implementation depended on extremely aggressive bonding pitch scaling, specifically reducing hybrid bonding pitch below 2µm while maintaining alignment overlay errors under 0.5µm.

According to He, the ratio between hybrid bonding pitch and top metal pitch needed to remain below three for LogicFolding to work effectively.

Huawei also described innovations involving through-silicon vias (TSVs), including sub-1.5µm critical dimensions and sub-6µm pitch structures.

The company claims these technologies have achieved extremely low failure rates and high repair yields through redundancy techniques.

Many of these technologies, Huawei said, are expected to enter wider production deployment from 2027 onwards.

Kirin 2026: The first LogicFolding processor
Huawei used the keynote to formally unveil its first commercial implementation of LogicFolding technology: Kirin 2026.

Scheduled for release later in 2026, the processor reportedly transitions from a conventional single-layer architecture to a double-layer folded design.

Huawei claims the shift produced dramatic gains in transistor density. According to the presentation, transistor density increased from 155 million transistors per square millimeter to 238 million in a single architectural generation.

The company also reported a 41% improvement in SoC performance-core power efficiency alongside a near-13% increase in maximum clock frequency.

He emphasized that these gains were achieved despite industry expectations that smartphone processors had already entered a performance saturation phase after previous Kirin generations.

The implication was clear: Huawei believes LogicFolding provides a viable route for continued performance scaling even as traditional transistor shrinkage slows.

SRAM and circuit-level folding
Huawei also provided technical examples illustrating how LogicFolding can improve specific subsystems.

One example focused on SRAM performance. As SRAM arrays increase in size, interconnect delays and communication overhead increasingly dominate total latency, often exceeding intrinsic transistor switching delays.

Huawei stated that in modern 1Mb SRAM arrays, more than 70% of total latency now originates from interconnect and communication delays.

Applying LogicFolding to SRAM structures reportedly reduced physical distances between memory arrays, peripheral circuits and processor cores while simultaneously lowering RC delays.

According to Huawei, this resulted in significant reductions in memory latency and energy per bit, while boosting SRAM operating frequency by more than 40%.

The company argued that such improvements would be difficult to achieve through process scaling alone.

Huawei also highlighted gains in processor clock distribution. In one example, folding architectures reportedly reduced clock buffer counts by over 50%, cut clock skew by 25% and shortened clock tree wire lengths by approximately 30%.

AI systems and “τ systems”

While much of the keynote focused on mobile processors, Huawei also devoted considerable attention to AI infrastructure.

He argued that AI systems represent a fundamentally different scaling problem from smartphones.

Modern AI systems consist of hundreds or thousands of heterogeneous chips operating in massively parallel configurations. In these environments, data movement increasingly dominates both energy consumption and system cost.

Huawei cited estimates suggesting more than 80% of energy in AI systems is consumed by moving data, while more than 70% of system cost is associated with data storage.

As a result, Huawei believes reducing communication time — not merely increasing raw compute capability — is becoming the defining challenge of AI infrastructure.

The company’s AI strategy is centered around what it calls “SuperNode” systems, including the Ascend 910C and newly announced Ascend 950 platforms.

Huawei explained that these systems are optimized differently for training and inference workloads, with each architecture tuned according to its own τ characteristics.

Inference systems, for example, place greater emphasis on low latency and rapid token generation, while training systems prioritize throughput and overlapping communication with computation.

Unified bus and “system as one chip”
One of the most notable AI-related announcements was Huawei’s new Unified Bus (UB) architecture.

Traditional multi-node AI systems often rely on multiple protocol layers and complex interconnect conversions, introducing latency, reliability challenges and cost overheads.

Huawei’s UB architecture attempts to unify communication protocols across both intra-box and inter-box interconnects using a peer-to-peer design.

The company claims this approach eliminates many protocol translation stages while simplifying deployment of ultra-large AI clusters.

Huawei also introduced memory-semantic communication capabilities within UB, enabling direct peer-to-peer data transfers without higher-layer protocol encapsulation.

According to He, this architecture allows AI systems to behave more like “System as One Chip,” reducing latency across large-scale deployments.

Optical interconnect and HiONE
Huawei also outlined its optical interconnect strategy for future AI infrastructure.

As AI bandwidth requirements rise into the multi-terabit-per-second range, the company argues that conventional electrical interconnects become increasingly impractical due to cable bulk, thermal constraints and signal integrity limitations.

To address this, Huawei developed HiONE, a high-density optical interconnect engine delivering 8Tbps bandwidth per AI chip.

The technology reduces electrical SerDes reach from approximately one meter to just a few centimeters while extending optical communication distances to around 100 meters.

Huawei believes this distributed optical approach enables high-density, gigawatt-scale AI data centers without concentrating excessive thermal and power density into individual racks.

Rethinking 2.5D packaging
Another major theme involved overcoming what Huawei described as the “2.5D scaling dilemma.”

In traditional 2.5D AI chip packaging, logic dies sit centrally within the package while memory stacks, interconnects and power delivery structures surround the edges.

As die sizes increase, compute capability scales quadratically with chip dimensions while edge-based memory bandwidth, power delivery and IO scale only linearly.

Huawei argues this mismatch creates a fundamental bottleneck for future AI scaling.

Its proposed solution is “System Folding,” where memory, power delivery and optical IO move vertically onto chip surfaces rather than remaining confined to package edges.

The company believes this architecture will allow all system resources to scale proportionally with compute density.

Huawei predicts that this approach could increase hardware integration density by more than 100 times by 2035.

Challenges ahead
Despite the ambitious vision, He acknowledged that major technical challenges remain.

One significant obstacle involves developing entirely new EDA tools and methodologies capable of supporting free-form folded logic design.

Huawei stated that it has already begun developing preliminary toolchains and plans to disclose further details in future technical publications.

Thermal management was identified as another critical challenge.

As chip power densities continue rising, Huawei believes thermal optimization must span every level of the system hierarchy, from individual devices to gigawatt-scale AI infrastructure.

The company discussed work involving integrated capacitors, thermal interface optimization and advanced cooling techniques.

A new semiconductor narrative
The keynote concluded with Huawei framing τ scaling as a universal and sustainable post-Moore scaling law.

According to He, Huawei has already designed and mass-produced 381 chips between 2020 and 2026 using this broader design philosophy across multiple industries and applications.

The company believes τ scaling provides a practical roadmap for continued semiconductor evolution over the coming decade, even as traditional geometric scaling becomes increasingly difficult and expensive.

Huawei’s projections include transistor density exceeding 400 million transistors per square millimeter, CPU frequencies surpassing 5GHz by 2031 and continued gains in smartphone and AI system performance.

Whether the broader semiconductor industry embraces Huawei’s τ scaling framework remains to be seen. However, the presentation clearly signaled Huawei’s intention to position itself not merely as a semiconductor company adapting to constraints, but as one attempting to redefine the future direction of semiconductor architecture itself.

In an era where the limits of Moore’s Law are becoming increasingly apparent, Huawei is betting that time — not just geometry — will define the next generation of computing.