Applied Materials unveils chip making systems for AI memory and packaging
Applied Materials has launched a range of new production systems aimed at the 3D chip architectures used in advanced AI hardware, spanning DRAM, advanced packaging and process control.
Applied Materials, Inc., has introduced a suite of new chipmaking systems for building the advanced 3D chip architectures that power next-generation AI.
Applied Materials said AI computing is increasingly limited by memory, as the growth in model size and data movement outpaces improvements in bandwidth, capacity and energy efficiency. According to the company, this "memory wall" is driving adoption of advanced packaging approaches such as high bandwidth memory (HBM) and 3D stacking, which sharply improve bandwidth and efficiency but add process complexity. Applied said its portfolio across DRAM, advanced packaging and process control is intended to help customers reach production faster and at higher yield.
Logic techniques move into DRAM
Epitaxy, the precise growth of a crystalline material in the transistor channel, has been used for years in leading-edge logic to lift performance beyond what geometric scaling alone allows. Applied said those techniques are now becoming important in DRAM peripheral transistors. The company pioneered silicon germanium epitaxy in transistor channels more than a decade ago with its Centura Prime Epi system.
Applied is now introducing an enhanced Centura Prime Epi system that selectively grows doped silicon germanium and silicon phosphorous in source and drain regions, combining strain engineering with precise doping control. The company said this raises drive current and transistor efficiency, allowing faster, more power-efficient DRAM operation for the bandwidth demands of HBM and next-generation DDR. The system also has a 20 per cent smaller footprint, supporting higher tool density and faster capacity scaling in DRAM fabs.
Dr Prabu Raja, president of the Semiconductor Products Group at Applied Materials, said the transistor and materials technologies that drove performance gains in leading-edge logic are becoming essential in DRAM. He said that as DRAM scales for HBM and AI workloads, the distinction between logic and memory process technology is converging, and that Applied's epitaxy leadership positions it to drive the transition.
New systems for advanced packaging
Applied said advanced packaging has become as strategically important as on-chip transistor scaling. Modern AI server chips combine multiple dies in a single package, with HBM stacking DRAM chips and connecting them using through-silicon vias (TSVs). Applied said it leads in process equipment covering most of the materials engineering steps needed to create the TSVs, copper pillars and microbumps that link stacked dies, and it introduced three systems for the most critical steps.
The Opta Quad platform, built on Applied's position in chemical mechanical planarisation (CMP), is designed for advanced packaging, where thicker films, longer polish times and tighter tolerances increase the risk of non-uniformity and yield loss. It monitors wafer conditions during polishing and adjusts in real time to improve within-wafer uniformity and thickness variation control. Applied said this is particularly important for hybrid bonding, an emerging 3D stacking technique that fuses copper wiring and surrounding dielectrics from two chips in a single step and requires near-perfect surface planarity.
Nokota VMax 2 is an electrochemical deposition (ECD) system for high-precision copper plating across next-generation packaging applications, from TSV fill for 3D stacking to fine-pitch interconnects such as microbump formation. It introduces Adaptive Pattern Tuning, which shapes the electric field to correct layout-driven variation and improve plating uniformity. Applied said uneven interconnects can leave gaps that prevent reliable contact between layers, making levelling across the wafer critical to stacking yield.
Producer Avila 2 is a plasma-enhanced chemical vapour deposition (PECVD) system addressing the warpage and deformation that arise when HBM dies are thinned to roughly one twenty-fifth the thickness of a standard wafer. Applied said the system deposits stress-balanced dielectric films around TSVs to improve mechanical stability, enabling reliable stacking of 12-layer, 16-layer and future high-layer-count HBM designs, as well as other advanced memory and logic integration schemes.
Raja said advanced packaging has become a primary driver of system-level performance, and that Applied's leadership in dielectric CVD, ECD and CMP, together with process integration expertise, gives customers the tools to scale 3D stacks reliably and at yield.
eBeam process control for packaging
Applied said advanced packaging fabs are meeting defect and metrology challenges once confined to wafer fabs, with features now below the resolution of optical inspection tools and previously tolerable particles now affecting yield. Because a single defect can require scrapping an entire HBM stack, it introduced two eBeam systems for packaging.
VeritySEM 7AP, the latest in Applied's critical dimension metrology range, measures features on thick, heterogeneous and highly warped substrates common in HBM and chiplet architectures. Applied said the systems reconfigure automatically for a range of sizes and materials while delivering sub-10nm sensitivity, far beyond optical tools.
SEMVision G7AP extends Applied's eBeam defect analysis platform into advanced packaging, enabling high-resolution defect review and automated classification across silicon, organic and glass substrates, helping distinguish critical defects from nuisance signals. Applied said the system is already in production at leading memory and logic manufacturers.
Keith Wells, group vice president and general manager of the Imaging and Process Control Group, said Applied has led in eBeam technology for decades and is transferring proven wafer-fab expertise into packaging, built for the substrates and defect challenges of 3D architectures.
