From 2D transistors to quantum processors: imec pushes semiconductor integration beyond conventional scaling

The semiconductor industry’s search for continued performance gains is increasingly extending beyond conventional transistor scaling. As artificial intelligence drives demand for greater compute density, memory capacity and bandwidth, while wireless systems move towards mmWave and sub-THz frequencies, semiconductor researchers are exploring new materials, architectures and integration techniques to extend what can be achieved within established manufacturing frameworks.

By IMEC

A series of recent developments from imec illustrates the breadth of this transition. The Belgian research and innovation centre has reported advances in heterogeneous integration of III-V chiplets on silicon, a new narrowband receiver architecture for ultra-wideband (UWB) systems, ferroelectric memory devices, 2D-material transistors, backside interconnects for three-dimensional integration and silicon-based quantum processors.

Although these technologies address very different applications, they share a common objective: finding ways to extract more functionality and performance from semiconductor systems without relying solely on conventional planar scaling.

The approaches range from integrating III-V materials with silicon CMOS and stacking devices vertically, to introducing atomically thin transition-metal dichalcogenides (TMDs), ferroelectric materials and silicon spin qubits into manufacturing flows increasingly based on 300mm semiconductor processing.

For the semiconductor industry, the significance lies not simply in the individual device demonstrations, but in the effort to make emerging technologies compatible with the infrastructure, design methodologies and process discipline of mainstream semiconductor manufacturing.

Heterogeneous integration moves towards system-level RF platforms
One of the clearest examples is imec’s development of a 300mm RF silicon interposer platform designed to integrate III-V chiplets with Si-CMOS.

The platform is being developed for applications including mmWave and sub-THz wireless systems and high-speed data-centre applications. It combines three developments: high-density embedded capacitors, a modelling framework for RF passive components and laser-assisted bonding for assembling III-V chiplets onto the interposer.

The underlying challenge is increasingly familiar. As wireless systems move to higher frequencies and electronic and photonic interfaces in data centres approach their performance limits, achieving high-performance signal handling can result in greater system complexity, power consumption, cost and physical footprint.

III-V materials such as indium phosphide (InP), gallium arsenide (GaAs) and gallium nitride (GaN) offer properties that are attractive for high-frequency and high-performance applications, while silicon CMOS provides the manufacturing scalability and cost advantages associated with the established silicon industry.

Rather than attempting to build every function in one semiconductor technology, heterogeneous integration allows different materials to be used where their properties are most advantageous. In this architecture, performance-critical functions can remain in compact III-V chiplets, while the silicon interposer provides low-loss interconnections and accommodates passive components.

The development builds on previous imec work. In 2024, the organisation demonstrated InP chiplet integration on a 300mm RF silicon interposer with negligible insertion loss at 140GHz. In 2025, the platform was extended to demonstrate record-low insertion loss up to 325GHz.

The latest work addresses some of the practical requirements for moving such an approach towards a more complete system platform.

Moving passives away from the chiplet
A significant element is the development of a new metal-insulator-metal capacitor, or MIMCAP, architecture.

Passive components can occupy a significant proportion of a chiplet’s area. Moving functions such as decoupling capacitors from the III-V chiplet to the interposer can therefore allow the active chiplet to become smaller while simultaneously making better use of the interposer’s available area.

According to imec, the new architecture produces a 10-to-100-fold increase in capacitance density compared with typical on-chip capacitors in III-V technologies.

The MIMCAP uses a high-k aluminium-hafnium-oxide dielectric combined with three-dimensional oxide-stud structures in the back-end-of-line.

The importance of the development is therefore architectural as much as device-specific. By treating the interposer as more than a passive routing layer, designers can distribute functionality across the package or system, placing each component where its characteristics are most useful.

That approach is increasingly relevant as semiconductor systems become more heterogeneous. Rather than treating the die as the sole location for functionality, advanced packaging allows the system architecture to incorporate different process technologies, materials and passive components.

Modelling becomes part of the integration challenge
Another component of the RF platform is a modelling framework for interposer passives.

At frequencies approaching the sub-THz range, small physical variations can have a significant impact on electrical performance. Designers therefore need models capable of predicting how passive components behave as their geometry changes.

Imec’s framework has been validated to approximately 300GHz and is designed to predict circuit performance without requiring every geometrical variation to be separately simulated or physically measured. The stated objective is to reduce development time while improving predictability.

The current framework focuses on transmission lines but is being extended towards inductors and MIM capacitors.

This illustrates an important characteristic of heterogeneous integration: the challenge is not simply manufacturing the individual components. It is creating a sufficiently accurate design environment in which their interactions can be predicted before fabrication.

Laser bonding addresses thermal constraints
The third element is assembly.

III-V chiplets may need to be integrated onto interposers that already contain temperature-sensitive materials and structures. Conventional bonding processes can impose thermal budgets that complicate this integration.

Imec has therefore demonstrated laser-assisted bonding for assembling III-V chiplets on a passives-rich RF interposer. The approach is intended to avoid damaging temperature-sensitive layers while maintaining the required alignment accuracy.

The reported alignment accuracy was below 600nm, with rotational misalignment below 0.05 degrees across 43 devices. RF measurements after assembly showed reflection below −15dB over the 110-170GHz range.

Together, the developments point towards a more complete manufacturing platform rather than a single component demonstration, with imec identifying low-volume manufacturing as a next stage in its technology development.

UWB moves towards longer-range positioning
A second imec development focuses on ultra-wideband wireless communication, where the challenge is not transistor scaling but maintaining reliable, precise positioning in increasingly crowded wireless environments.

Imec has developed a narrowband receiver compliant with the narrowband assistance mechanism defined in the forthcoming IEEE 802.15.4ab UWB standard. The implementation is reported to enable a fourfold increase in ranging distance, while a complete transceiver architecture combining receiver, transmitter and standard innovations has demonstrated up to a 32-fold improvement in ranging performance.

UWB is already being deployed in smartphones, wearables, automotive systems and IoT devices, but range, scalability and resistance to interference remain challenges, particularly in dense wireless environments.

The IEEE 802.15.4ab approach introduces narrowband assistance, using signalling in the 5-6GHz range alongside UWB for discovery, synchronisation and coordination. The narrowband link can allow systems to operate at lower signal levels while supporting greater range and multi-user scalability.

This creates a demanding receiver design problem. The receiver needs a sufficiently low noise figure to detect weak signals, while also tolerating strong Wi-Fi signals operating in nearby or overlapping frequency bands.

Imec’s solution uses a second-order transimpedance amplifier with controlled filtering, implemented in a 22nm CMOS process. The architecture suppresses strong out-of-band interference early in the signal chain while maintaining sensitivity to the desired signal.

An adaptive clip detector adds another layer of control. When strong interference is detected, the receiver can switch to a more robust operating mode with additional filtering and gain control. Under lower-interference conditions, it can remain in a lower-power mode.

The reported receiver consumes less than 6mW, achieves a 9dB improvement in dynamic range over state-of-the-art implementations, has a 3.2dB noise figure and tolerates Wi-Fi blockers around −32dBm.

Potential applications include robot-to-robot coordination and AR glasses that need to understand and interact with their physical surroundings. The work is therefore relevant not only to conventional wireless connectivity but also to emerging systems in which precise spatial awareness is part of the computing architecture.

Ferroelectric devices target AI-era memory requirements
Memory is another area where conventional scaling is encountering increasingly difficult constraints.

AI workloads are creating demand for substantially greater memory capacity, bandwidth and energy efficiency. At the same time, technologies such as DRAM and SRAM are becoming more difficult to scale using established approaches.

Imec is consequently investigating ferroelectric materials as a route towards low-voltage and high-density memory.

Recent results cover two complementary device concepts: ferroelectric capacitors and vertically stacked ferroelectric field-effect transistors (FeFETs). The former could support future DRAM-like memory concepts, while the latter could enable compact three-dimensional memory architectures.

The capacitor work demonstrates operation at approximately 1.3V while maintaining remnant polarisation above 40μC/cm² and endurance of at least 10¹³ cycles.

Separately, imec has demonstrated vertically stacked IGZO-based FeFETs, including a five-word-line stack fabricated on 300mm wafers. A dual-gate architecture is used to improve erase efficiency.

The significance of the vertical architecture is straightforward: increasing memory density does not necessarily have to depend on making every individual device smaller. Devices can also be stacked.

This is increasingly important as three-dimensional integration becomes a recurring theme across logic, memory and advanced packaging. Ferroelectric devices offer another route towards exploiting vertical space while potentially reducing operating voltage.

Imec describes the two research tracks as complementary. The same materials and integration knowledge can inform both capacitor and FeFET development, while three-dimensional integration techniques developed for FeFETs can potentially be applied to future ferroelectric capacitor arrays.

The technologies remain at the research stage. Remaining challenges include FeFET endurance and erase performance, together with further voltage scaling and reliability optimisation for ferroelectric capacitors. The next steps include system-level evaluation and development of fully integrated three-dimensional memory architectures.

2D materials take another step towards the fab
Perhaps one of the most consequential developments in the portfolio is the demonstration by imec, ASML and TSMC of scaled transistors based on two-dimensional materials on 300mm wafers.

Transition-metal dichalcogenides such as MoS₂, WS₂ and WSe₂ have attracted attention because their atomically thin channels offer strong electrostatic control at very small dimensions.

The difficulty has been moving from laboratory-scale demonstrations to manufacturing processes compatible with semiconductor industry requirements.

The latest work demonstrates nFETs using MoS₂ and pFETs using WS₂ or WSe₂ with a 50nm contacted poly pitch (CPP), patterned using EUV lithography. Imec describes this as the first demonstration of scaled n- and pFETs based on these materials at this CPP.

The achievement is particularly significant because CPP includes both gate length and source/drain contact length. Contacts have traditionally presented a major scaling challenge for 2D devices: while the atomically thin channel can be made very small, the surrounding contact structures can consume substantially more space.

The reported process achieved 50nm CPP without compromising the performance of the 2D n- and pFETs. Single-patterning EUV lithography was used in collaboration with ASML.

The devices also demonstrated low off-current at zero gate voltage, with pFETs based on WSe₂ performing close to the best reported laboratory devices.

Importantly, the n- and pFETs were integrated on the same 300mm wafer. The reported operational transistor rate was 94%, with an Imax/Imin ratio greater than 10⁵.

The manufacturing approach uses a reverse thin-film transistor flow in which the TMD channel is transferred onto pre-patterned tungsten-filled trenches acting as contacts, followed by deposition of an overlapping gate.

The combination of 300mm processing, EUV patterning and CMOS-like integration makes the work relevant to the longer-term question of whether 2D materials can become part of an industrial technology roadmap rather than remaining primarily laboratory devices.

The research is also being positioned for applications beyond conventional frontside logic. Imec identifies potential roles for 2D materials in ultra-scaled logic, back-end-of-line integration and wafer backside applications.

Backside connectivity becomes a critical part of 3D scaling
As semiconductor architectures become increasingly three-dimensional, the interconnections between the front and back of the wafer become just as important as the devices themselves.

Imec and Sony Semiconductor Solutions have demonstrated a new approach to highly dense backside through-silicon vias (TSVs), using a self-aligned local backside dielectric isolation, or local BDI, module.

The approach is intended to provide dense front-to-back connectivity while reducing some of the electrical and manufacturing constraints associated with conventional via-middle TSV structures.

The resulting TSVs reportedly have lower aspect ratio, three times lower resistance, a three-times larger overlay window and lower leakage compared with conventional via-middle TSVs.

The issue is rooted in the geometry of conventional TSVs. High-density front-to-back connections can require narrow vias passing through relatively thick silicon, creating challenges for metallisation, alignment and electrical performance.

The local BDI approach instead forms a self-aligned isolation structure locally at the overlap between the TSV and active frontside region. The resulting geometry permits wider TSV connections.

Imec reports a 50% larger bottom and top critical dimension compared with the relevant via-middle approach, together with a threefold improvement in resistance. The demonstrated overlay tolerance extends to 30nm for a standard-cell configuration with 115nm cell height.

Another important characteristic is that the process can operate through bulk silicon up to 500nm thick. This could be relevant to applications such as DRAM, where a relatively thick silicon layer may remain on the backside.

The development highlights a broader shift in semiconductor integration. Backside processing is increasingly becoming an active component of device architecture rather than simply a packaging consideration.

For advanced logic and memory, the ability to move power, signals and functionality through the wafer can provide additional architectural freedom as frontside routing becomes increasingly constrained.

Silicon quantum computing enters the 300mm manufacturing equation
The most unconventional development in the group moves beyond conventional semiconductor computing altogether.

Imec and Diraq have demonstrated coherent operation and readout of an eight-qubit silicon MOS spin-qubit array fabricated on imec’s 300mm CMOS-compatible spin-qubit platform.

The result extends previous work beyond individual and two-qubit devices and provides evidence that increasingly complex silicon quantum systems can be manufactured using industrial semiconductor processing.

Silicon spin qubits are attractive partly because they can potentially exploit semiconductor industry’s existing manufacturing infrastructure, supply chains and process expertise.

The new eight-qubit linear array builds on a 2025 demonstration showing that industrially manufactured silicon spin qubits could achieve fidelity levels relevant to quantum error correction. The latest work extends that manufacturing approach to a larger array while maintaining the coherence and controllability required for future scaling.

An important aspect of the demonstration is the scaling of the readout architecture. The larger array does not require a corresponding increase in sensor count, wiring density or thermal load. Such scaling characteristics are important because wiring and readout can become significant constraints as quantum processors grow.

The devices were manufactured using imec’s 300mm silicon spin-qubit platform, built around nearly a decade of process optimisation and engineering.

That connection to established semiconductor manufacturing is central to the significance of the work. Quantum computing has often been discussed as a fundamentally different manufacturing challenge, but silicon spin qubits create the possibility of using techniques derived from mainstream CMOS production.

The eight-qubit demonstration is not, by itself, a large-scale quantum processor. However, it addresses an important intermediate question: whether semiconductor manufacturing can support increasingly complex quantum devices without losing the properties required for quantum operation.

Integration is becoming the industry’s new scaling language

Taken together, these developments point towards a semiconductor technology landscape in which “scaling” increasingly means more than shrinking the transistor.

The III-V interposer work uses heterogeneous integration to combine different semiconductor materials. The 2D-material programme introduces atomically thin channels into 300mm processing. Ferroelectric memory explores new materials and vertical architectures. The Sony- imec TSV work develops new routes for connecting frontside and backside circuitry. The UWB receiver demonstrates how architectural innovation can improve wireless performance within an established CMOS process. The silicon quantum work applies semiconductor manufacturing to an entirely different computing paradigm.

The common denominator is integration.

For decades, semiconductor progress has been closely associated with increasing transistor density through lithographic scaling. That remains important, but the economics and physical constraints of advanced nodes are encouraging a more distributed approach.

Performance-critical functions can be fabricated using different materials and assembled together. Passive components can be moved from chiplets onto interposers. Memory can be stacked vertically. Electrical connections can be routed through the backside of the wafer. Novel channel materials can be introduced where silicon becomes increasingly constrained. Quantum devices can be fabricated using CMOS-compatible infrastructure.

This is not necessarily a replacement for transistor scaling. Rather, it represents an expansion of the semiconductor design space.

From research demonstration to manufacturing platform
The repeated appearance of 300mm processing across these developments is particularly significant.

A technology can demonstrate impressive device performance on a laboratory wafer while remaining far from practical semiconductor manufacturing. Industrial adoption requires reproducible processing, alignment, yield, process control, compatible materials, equipment availability and eventually economic viability.

The work on 2D materials explicitly addresses this lab-to-fab transition. The III-V interposer programme similarly combines device, passive, modelling and assembly technologies into a more complete platform. The quantum work applies CMOS-compatible manufacturing to increasingly complex qubit arrays.

In each case, the question is shifting from “can the device work?” towards “can the technology be integrated, manufactured and scaled?”

That distinction will become increasingly important as semiconductor companies seek alternatives and complements to conventional scaling.

The technologies described here remain at different levels of maturity. Some, such as the RF interposer and UWB receiver developments, are being developed towards application and industry integration, while the ferroelectric memory, 2D transistor and quantum computing programmes remain more firmly in the research and technology-development phase.

Nevertheless, the direction is clear.

The next generation of semiconductor systems is likely to depend on multiple forms of integration operating simultaneously: heterogeneous materials, chiplets, three-dimensional stacking, backside processing, advanced packaging, novel memory devices and increasingly specialised computing architectures.

A broader definition of semiconductor innovation
The significance of imec’s latest research is therefore less about any single breakthrough than about the convergence of multiple technology paths.

AI is creating pressure for more compute and memory capacity. High-frequency wireless systems are pushing semiconductor devices and interconnects towards mmWave and sub-THz operation. Data-centre architectures are demanding increasingly efficient signal handling and power delivery. Meanwhile, applications such as robotics and augmented reality require low-power sensing, positioning and communication.

Meeting these requirements will require semiconductor technologies that can combine different materials and functions while remaining compatible with manufacturing ecosystems capable of producing them at scale.

The III-V RF platform addresses this through chiplets and interposers. The UWB work combines narrowband assistance with UWB positioning. Ferroelectric devices explore alternative routes to memory density and low-voltage operation. 2D materials seek to extend transistor scaling beyond conventional silicon channels. Backside TSVs provide additional connectivity for three-dimensional systems. Silicon spin qubits demonstrate how CMOS manufacturing can be extended into quantum computing.

The unifying idea is that future semiconductor performance may increasingly come from integration at multiple levels, rather than from transistor dimensions alone.

For the semiconductor industry, that creates a more complicated technology roadmap, but also a wider range of opportunities. The challenge will be converting promising device concepts into processes that can operate within the economic, manufacturing and reliability constraints of the semiconductor supply chain.

The latest research suggests that this transition is already under way. The 300mm wafer is becoming a common platform not only for conventional CMOS, but also for heterogeneous chiplets, emerging memory, 2D materials, backside interconnects and silicon quantum devices.

That may ultimately prove to be one of the defining characteristics of the post-planar semiconductor era: not a single successor to CMOS, but an increasingly diverse set of technologies connected by sophisticated integration and manufacturing platforms.