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Considerations Of R&D Scale CMP Processing And It's Use In Novel Applications

Getting chemical mechanical planarisation (CMP) right is one of the key factors in successful back-end of line processing. James J McAneny and John H Welty of Logitech describe how a small scale CMP system can be used in an R&D environment to test new processes...
Research and development scale chemical mechanical planarisation (CMP) needs systems with industrial-level process control and quality. R&D CMP has further to be able to handle and evaluate novel applications and materials (slurries, pads or templates). Such as platform must be able to handle any combination of wafers or die without radical alterations to its construction. Researchers may want to carry out wide ranging work in a "design of experiments" (DoE) scenario or small scale empirical testing of distinct new processes. Reduced consumable consumption and costs are also clearly desirable.



Early considerations



Initially, the model type, construction materials, control variables had to be established in order to design a CMP platform that would enable the range of experiments to be covered.



The construction materials of the machine had to include sufficient resistance to acidic and alkaline polishing slurries and provide a simple, easily interchangeable slurry dispensing system (Fig.1) should multiple slurries or flushing solutions be necessary in the process. A method of storing all of the process parameters would also be required to allow repeatability when running any DoE analysis.











Fig.1:
Multiple slurry manifold

(number of pipes optional)



The rotary platen model was chosen over the linear polisher as this was more popularly recognised in many polishing applications and offered a simpler layout for monitoring the process.



From the numerous papers published over the years it became apparent that the main parameters that could be varied were already well documented and considerable experimentation and testing had already been carried out in both blanket oxide polishing and patterned oxide polishing. These effects were considered when the project was planned.



Prior to this project commencing, extensive research had been already been carried [1]. This established the full range of CMP processes in the market today and uncovered a surprising range of applications including metallisation, shallow trench isolation, intermetal dielectric and noble metals. It was therefore important to consider this range of requirements when researching the variables that are significant in terms of the effect on the particular surface in process. Examples of two typical applications - SEMI standard wafers and individual wafer die - were used to focus on the process variables for emerging technologies and materials.



The platen to wafer ratio was established to optimise the range of wafer diameters likely to be run on the platform and was kept to a minimum without compromising the control over the wafer topography during processing. This was completed using a 500mm-diameter platen and two carrier heads at 125mm and 250mm diameters.



To allow control over the relative linear velocities of the carrier and platen which in turn would have a proportional effect on the material removal rate covered by Preston's equation [2], the drives were set up to allow variable speed in either clockwise or counter-clockwise directions. As this is linked with the applied down force, this was also required to be variable and repeatable.



Preparation and start



A silicon wafer of 75mm diameter and a fabricated IC chip of 7x7mm were chosen as suitable test wafers for these experiments. Two template carrier heads of 125mm outside diameter were fabricated along with two template designs of the same outside diameter, but manufactured to accommodate the above wafer dimensions (Figures 2 and 3). The wafers were measured prior to processing and the parameters set up based on these values (Tables 1 and 2). Two pad types were chosen to suit removal, separately, of oxides and metals. The slurries chosen were a neutral colloidal silica (pH7) and an alkaline colloidal silica (pH10.2). Both slurries had a particle size of 32nm. The differing geometries of the wafers also required that the templates and pads used were of different design.











Fig.2:
Template design











Fig.3:
125mm Template carrier heads with three template options fitted for:
a 100mm, 75mm wafer

or custom die



For the complete wafer a conventional 75mm wafer pocket template was used but for the part wafer die a custom template was necessary to suit the specific dimensions of the chip.



Some of the significant parameters, which will affect within-wafer non-uniformity (WIWNU) and affect wafer-to-wafer non-uniformity (WTWNU), are polishing platen rotational speed, carrier rotational speed, carrier rotation relative to the platen direction, carrier down force, wafer back pressure, slurry flow rate, polishing platen surface condition/wear and polishing platen temperature.



Each of these variables require a substantial number of wafer process trials to fully gauge the extent of the resultant effect of each or the compound effect of various combinant adjustments. Work is an ongoing on these aspects.



To aid the monitoring of any change occurring during the processes and allow in situ conditioning two additional systems were added to the machine platform.



* Custom software was written specifically to measure any change in the main drive and carrier parameters. This software was written to be user definable to allow monitoring and recording of the motor current and voltages while processing and acts as a means of end point detection using the effect of the co-efficient of friction on different materials [2].



* A conditioner arm was added to allow in-situ or ex-situ conditioning of the polishing pads. Any generic diamond conditioner or other disc can be accommodated on the arm by the addition of a simple retainer.



To simplify the control interface, a simple joystick driven menu was used and custom software written to enable each process recipe to be stored for later analysis of each parameter change. The machine was fitted with two main screen options to facilitate process trials and allow storage of the data for repeated runs (Figures 4 and 5).











Fig.4:
Typical polishing pad for CMP processes






Variables under test



The polishing platen rotational speed was established to be variable from 20rpm to 160rpm to allow the required range of variation in the process. Most of the polishing pads and slurries on the market can be used successfully at these speeds by creating a layer of free flowing abrasive fluid on the surface of the polishing platen.



In order to combine the correct wafer and slurry directions of motion, it was necessary to allow the carrier rotation a similar range of variability in speed from 20rpm to 130rpm. This has the effect either of equalising the centre to edge removal rates, preferentially removing more material from the edge than the centre or preferentially removing more from the centre than the edge.



It can be advantageous in specific processes to have the platen and the carrier rotating either in the same or contrary directions. This depends on which of the various pads is being used as well as the required slurry motion.



The variation in wafer diameters, materials, bow, layer thickness and initial topography will all have an effect on the outcome of the final surface condition. To provide a range of control on how the wafer is applied to the surface of the polishing pad the down force pressure must be repeatably variable.



To complement the preset down force on the carrier, the options of vacuum or back pressure must be available to compensate for the initial wafer conditions. This yet again must be variable to allow alterations to suit individual wafers that have distinctly different start conditions. The vacuum pressure will allow the wafer back surface to be pulled upwards and the vacuum pattern on the template will determine the wafer area that will be varied the most. Equally, the application of positive pressure behind the wafer will also induce a shape change by pushing areas of the wafer forward with greater force against the polishing pad.



With the combination of all these parameters, the slurry flow rate must also be varied to keep a sufficient flow rate of slurry on the pad and to ensure that no dry areas appear during processing. If the slurry flow is insufficient or does not reach all of the pad surface in contact with the wafer, then the pad will make direct contact with the wafer with no fluid medium between them. This will result in scratching and surface damage, thus degrading the CMP process.



As each process is undertaken the pad will undergo wear and contamination from the slurry drying out, lumping together or impacting in the surface. These effects will then change the resultant CMP effect on the wafer or wafers if left unchecked and will reduce the pad life significantly. The conventional method of prolonging pad life and refreshing the surface is to use a conditioning tool. These tools are usually manufactured from a diamond matrix which will cut the pad surface and remove debris embedded in the surface as well as improving the pad flatness - an important parameter, as the average effect of this provides the resultant flat wafer surface.



Acknowledgments:

R.Coull, M.Kennedy, D.Robertson, J.N.Baraclough, Logitech.



References:



[1] R.Coull, Logitech, A Review and Investigation of the Chemical Mechanical Planarisation of thin Silicon Dioxide Films, Napier University Library, (2001).



[2] F.W.Preston, J. Soc. Glass Technology, 11, 247(1927).



[3] Jia-Zhen Zheng, Vincent Huang S.K., Mark Toh W.S., Charlie Tay W.S., Feng Chen, and Bin-Bin Zhou, Optimization of Pad Conditioning for Stable Oxide CMP Process, February 1997, CMP-MIC Conference.



[4] Sung Hoon Lee, Hae Do Jeong, The New Concept of Conditioner for CMP1998, February 1998, CMP-MIC Conference.



[5] Misuo Sugiyama and Hatuyuki Arai, Stabilization of CMP Process by IN_SITU Dressing, 1997, ABRASIVE TECHNOLOGY SEMICON



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