News Article
Are you taking advantage of silicon suppliers?
Technology changes in the semiconductor market is forcing device makers to partner with silicon wafer manufacturers to achieve the performance needed to move forward. Those who take advantage of the new reality will realise a competitive edge and reap the subsequent rewards, writes Dr Bruce K Kellerman of MEMC Electronic Materials
The semiconductor industry is continually evolving. Today we are undergoing more than a simple evolutionary change - it is a change in the technology itself. This technological change requires a fundamental shift in the way that business is conducted. Some device makers realise this and are taking advantage of new opportunities and realising the profits. Others are not. The best way to understand the current shift is to review the recent past and objectively evaluate how we have been conducting business and, most importantly, how we have been viewing our silicon suppliers.
In the early days of our industry (the 1960s and 1970s), device makers and silicon manufacturers learned together. The industry was new, and the issues were new. Understanding fundamental silicon materials science issues was imperative during the early stages of high volume manufacturing. Thanks to collaborative efforts, involving relatively large R&D budgets and numerous universities, the industry quickly identified solutions to materials-related challenges. As a result, the number of starting-material related issues steadily decayed as the industry matured.
Once the chemistry and physics of building devices were sufficiently understood, device makers focused on building increasingly smaller devices. All development activity was above the gate, and device manufacturers made relatively few changes to the materials used. The description that best classifies this recent past (1980s and 1990s) is the period of scaling.
During this period, the industry operated differently. The number of collaborations declined, and device makers faced nearly every challenge on their own. This worked because the challenges were in their domain, and they could afford to do so. Silicon wafers were viewed simply as the initial building block. Silicon was quickly considered a commodity.
And why not? Device manufacturers could order and receive the “same” product from a number of different silicon suppliers. Although they did not actually receive identical products, wafers from different silicon suppliers performed comparably. Purchase decisions were then made on price alone.
However, viewing silicon as a commodity prevents device makers from realising the value of silicon. Basing purchases solely on price is not a healthy way for our highly technical industry to operate, and the consequences are apparent. The number of silicon manufacturers has rapidly declined, as competition on price increased. Before 1990, more than 20 silicon suppliers existed, producing the standard 150mm diameter products. In 1993, the standard was 200mm diameter wafers with 10 silicon suppliers. Today, 7 silicon suppliers (and only 4 major ones) produce 300mm diameter wafers in significant volumes.
And the shakeout is not complete. The silicon wafer industry is still adjusting to the overcapacity that has plagued it since 1997. In fact, overcapacity is precisely why attempts to extract more value from the silicon link in our chain have proven fruitless.
In recent years, diameter changes and the accompanying parametric improvements that enhance design shrinks have been the most valued silicon technology. But, we must be careful. Diameters may not increase again. Even if they do, silicon manufacturers do not realise the same cost reduction opportunities when transitioning to larger diameters. This is the major reason why the silicon wafer industry has been, on average, unhealthy. We cannot continue this way.
How can we break this cycle and continue to increase value while decreasing costs? We must shift our mindset back into a strategic, collaborative problem-solving mode and out of the tactical, price-driven product-delivery industry of the recent past. We must look at all alternatives, not just cost of ownership. Contrary to some thinking, there are alternative wafer solutions that provide tangible benefits. Material properties are, once again, becoming increasingly important, and differences among silicon wafers from various vendors are becoming evident.
Some device makers have recognised this, made the mental leap and are reaping the benefits. They have realised that silicon can enable advanced technologies. For example, MEMC has developed a novel approach called Magic Denuded Zone (MDZ) that provides reproducible, reliable internal gettering. Wafers treated with the MDZ process will maintain a pre-determined level of bulk microdefects (BMDs), which provide the internal gettering, that is largely independent of the initial level of interstitial oxygen. Figure 1 compares the level of BMDs as a function of oxygen content in wafers with and without MDZ. In addition, the MDZ process furnishes device makers with a gettering solution for all applications. Figure 2 reveals a consistent level of BMDs located a safe distance from the device region for three different integrated circuit thermal cycles. MDZ is a drop-in solution that eliminates the need for low temperature oxygen precipitate nucleation and high temperature oxygen out-diffusion. Figure 3 depicts a representative thermal cycle from a fab producing chip from an analogue-type process. In this example, the customer was able to reduce the overall thermal cycle, by eliminating the two steps mentioned above, from approximately 2900 minutes, when processing wafers without MDZ, to only 1800 minutes, when processing wafers with MDZ: a reduction in the thermal budget of nearly 40%. This translates directly into reduced capital expenditures. On the processing side, device reliability and yield improvements have been demonstrated - in excess of 10% on specific devices. Truly, all silicon wafers are not created equal.
As we move forward, the opportunities are even greater. In order for device makers to continue their aggressive path of scaling, they must overcome the physical limitations inherent with traditional materials. Bulk silicon in its current form will not be the starting material of the future. Advanced materials such as silicon-on-insulator (SOI), strained silicon (sSi) and strained silicon on insulator (sSOI) are gaining widespread acceptance in the industry. Many device makers, from leading-to-trailing edge, are using advanced starting materials to enhance performance or to extend the life span of current toolsets.
For example, device makers incorporating SOI as the starting material are realising a 20-35% performance gain at the same power or, in some cases, a 2x-3x lower power at the same performance mainly due to a reduction in junction capacitance and in leakage current. Analogously, CMOS devices properly fabricated on a layer of sSi will operate with a clock speed 1-1.5 device generations higher. Since speed and power are correlated, a similar sSi CMOS device would operate at the same clock speed but consume approximately 50% less power. Although device makers may not agree on the timing, all agree that advanced materials will be needed. Together, the device makers and silicon manufacturers will resolve integration issues surrounding advanced materials.
Another emerging area is the CMOS integration of radio frequency (RF) transceiver devices operating in the GHz frequency range. Normal silicon wafer substrate resistivity ranges span from about 5mΩcm on heavily doped epi substrates to 30Ωcm on polished wafers. Although heavily doped substrates offer useful protection against latch-up, digital CMOS device design and performance has not been strongly coupled directly to substrate resistivity. This is changing. Wireless chip designs now benefit significantly from higher silicon substrate resistivity level in a variety of ways, including performance improvements of passive components such as inductors, and substrate electrical isolation between the integrated digital, RF and analogue components. Substrate resistivities greater than 40Ωcm are now required, and in some cases resistivities in excess of 1000Ωcm will be needed. Only by properly using the properties and features of all starting materials can we make significant, rather than incremental, advances.
Obviously, the introduction and integration of advanced materials will necessitate collaborations and close alignments. In the past, device makers may have been able to create value internally, both because they had the necessary resources and because the scope of the challenge was limited to their territory. Today, silicon suppliers must be involved in the problem-solving venture. Today’s challenges reflect those encountered during the early days of the industry – the integration, development and effective use of new materials. As a result, the value creation opportunity is migrating back to the silicon supplier.
Every device maker must make a decision - continue to create value internally and view silicon wafers as a commodity, or work with and take advantage of silicon suppliers. Continuing in the old ways may work, but only in the short term. Eventually, you must change your way of doing business, or the market will change it for you. Device makers who choose to partner with the right silicon wafer manufacturer and take advantage of the new reality will realise a competitive edge and reap the subsequent rewards.
Author details:
Dr Bruce K Kellerman is director of Applications Research for MEMC Electronic Materials in St Peters, Missouri. He joined MEMC as an applications engineer in 1996. Before joining MEMC he held a post-doctoral position in the Semiconductor Physics department at Sandia US national laboratory in Albuquerque, New Mexico.
Dr Kellerman received a BSc in Chemistry from Rhodes College in Memphis, Tennessee, in 1989 and a PhD in Chemistry from the University of Texas at Austin in 1995. He is a member of the American Chemical Society and the American Vacuum Society.
In the early days of our industry (the 1960s and 1970s), device makers and silicon manufacturers learned together. The industry was new, and the issues were new. Understanding fundamental silicon materials science issues was imperative during the early stages of high volume manufacturing. Thanks to collaborative efforts, involving relatively large R&D budgets and numerous universities, the industry quickly identified solutions to materials-related challenges. As a result, the number of starting-material related issues steadily decayed as the industry matured.
Once the chemistry and physics of building devices were sufficiently understood, device makers focused on building increasingly smaller devices. All development activity was above the gate, and device manufacturers made relatively few changes to the materials used. The description that best classifies this recent past (1980s and 1990s) is the period of scaling.
During this period, the industry operated differently. The number of collaborations declined, and device makers faced nearly every challenge on their own. This worked because the challenges were in their domain, and they could afford to do so. Silicon wafers were viewed simply as the initial building block. Silicon was quickly considered a commodity.
And why not? Device manufacturers could order and receive the “same” product from a number of different silicon suppliers. Although they did not actually receive identical products, wafers from different silicon suppliers performed comparably. Purchase decisions were then made on price alone.
However, viewing silicon as a commodity prevents device makers from realising the value of silicon. Basing purchases solely on price is not a healthy way for our highly technical industry to operate, and the consequences are apparent. The number of silicon manufacturers has rapidly declined, as competition on price increased. Before 1990, more than 20 silicon suppliers existed, producing the standard 150mm diameter products. In 1993, the standard was 200mm diameter wafers with 10 silicon suppliers. Today, 7 silicon suppliers (and only 4 major ones) produce 300mm diameter wafers in significant volumes.
And the shakeout is not complete. The silicon wafer industry is still adjusting to the overcapacity that has plagued it since 1997. In fact, overcapacity is precisely why attempts to extract more value from the silicon link in our chain have proven fruitless.
In recent years, diameter changes and the accompanying parametric improvements that enhance design shrinks have been the most valued silicon technology. But, we must be careful. Diameters may not increase again. Even if they do, silicon manufacturers do not realise the same cost reduction opportunities when transitioning to larger diameters. This is the major reason why the silicon wafer industry has been, on average, unhealthy. We cannot continue this way.
How can we break this cycle and continue to increase value while decreasing costs? We must shift our mindset back into a strategic, collaborative problem-solving mode and out of the tactical, price-driven product-delivery industry of the recent past. We must look at all alternatives, not just cost of ownership. Contrary to some thinking, there are alternative wafer solutions that provide tangible benefits. Material properties are, once again, becoming increasingly important, and differences among silicon wafers from various vendors are becoming evident.
Some device makers have recognised this, made the mental leap and are reaping the benefits. They have realised that silicon can enable advanced technologies. For example, MEMC has developed a novel approach called Magic Denuded Zone (MDZ) that provides reproducible, reliable internal gettering. Wafers treated with the MDZ process will maintain a pre-determined level of bulk microdefects (BMDs), which provide the internal gettering, that is largely independent of the initial level of interstitial oxygen. Figure 1 compares the level of BMDs as a function of oxygen content in wafers with and without MDZ. In addition, the MDZ process furnishes device makers with a gettering solution for all applications. Figure 2 reveals a consistent level of BMDs located a safe distance from the device region for three different integrated circuit thermal cycles. MDZ is a drop-in solution that eliminates the need for low temperature oxygen precipitate nucleation and high temperature oxygen out-diffusion. Figure 3 depicts a representative thermal cycle from a fab producing chip from an analogue-type process. In this example, the customer was able to reduce the overall thermal cycle, by eliminating the two steps mentioned above, from approximately 2900 minutes, when processing wafers without MDZ, to only 1800 minutes, when processing wafers with MDZ: a reduction in the thermal budget of nearly 40%. This translates directly into reduced capital expenditures. On the processing side, device reliability and yield improvements have been demonstrated - in excess of 10% on specific devices. Truly, all silicon wafers are not created equal.
As we move forward, the opportunities are even greater. In order for device makers to continue their aggressive path of scaling, they must overcome the physical limitations inherent with traditional materials. Bulk silicon in its current form will not be the starting material of the future. Advanced materials such as silicon-on-insulator (SOI), strained silicon (sSi) and strained silicon on insulator (sSOI) are gaining widespread acceptance in the industry. Many device makers, from leading-to-trailing edge, are using advanced starting materials to enhance performance or to extend the life span of current toolsets.
For example, device makers incorporating SOI as the starting material are realising a 20-35% performance gain at the same power or, in some cases, a 2x-3x lower power at the same performance mainly due to a reduction in junction capacitance and in leakage current. Analogously, CMOS devices properly fabricated on a layer of sSi will operate with a clock speed 1-1.5 device generations higher. Since speed and power are correlated, a similar sSi CMOS device would operate at the same clock speed but consume approximately 50% less power. Although device makers may not agree on the timing, all agree that advanced materials will be needed. Together, the device makers and silicon manufacturers will resolve integration issues surrounding advanced materials.
Another emerging area is the CMOS integration of radio frequency (RF) transceiver devices operating in the GHz frequency range. Normal silicon wafer substrate resistivity ranges span from about 5mΩcm on heavily doped epi substrates to 30Ωcm on polished wafers. Although heavily doped substrates offer useful protection against latch-up, digital CMOS device design and performance has not been strongly coupled directly to substrate resistivity. This is changing. Wireless chip designs now benefit significantly from higher silicon substrate resistivity level in a variety of ways, including performance improvements of passive components such as inductors, and substrate electrical isolation between the integrated digital, RF and analogue components. Substrate resistivities greater than 40Ωcm are now required, and in some cases resistivities in excess of 1000Ωcm will be needed. Only by properly using the properties and features of all starting materials can we make significant, rather than incremental, advances.
Obviously, the introduction and integration of advanced materials will necessitate collaborations and close alignments. In the past, device makers may have been able to create value internally, both because they had the necessary resources and because the scope of the challenge was limited to their territory. Today, silicon suppliers must be involved in the problem-solving venture. Today’s challenges reflect those encountered during the early days of the industry – the integration, development and effective use of new materials. As a result, the value creation opportunity is migrating back to the silicon supplier.
Every device maker must make a decision - continue to create value internally and view silicon wafers as a commodity, or work with and take advantage of silicon suppliers. Continuing in the old ways may work, but only in the short term. Eventually, you must change your way of doing business, or the market will change it for you. Device makers who choose to partner with the right silicon wafer manufacturer and take advantage of the new reality will realise a competitive edge and reap the subsequent rewards.
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Fig.1: Standard vs. MEMC’s Magic Denuded Zone (MDZ) wafers after full thermal processing. Resulting bulk microdefect (BMD) density is largely independent of intial interstitial oxygen (Oi) |
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Fig.2: MDZ – independent of application. Despite large differences in process details, precipitate free zone (PFZ) depth and BMD density are nearly the same for all |
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Fig.3: MDZ reduces device processing time. Example from fab running analogue-type process. MDZ saves time by reducing the need for initial oxygen out-diffusion and the need for re-nucleation to achieve target precipitate densities |
Author details:
Dr Bruce K Kellerman is director of Applications Research for MEMC Electronic Materials in St Peters, Missouri. He joined MEMC as an applications engineer in 1996. Before joining MEMC he held a post-doctoral position in the Semiconductor Physics department at Sandia US national laboratory in Albuquerque, New Mexico.
Dr Kellerman received a BSc in Chemistry from Rhodes College in Memphis, Tennessee, in 1989 and a PhD in Chemistry from the University of Texas at Austin in 1995. He is a member of the American Chemical Society and the American Vacuum Society.
