HIGH PRODUCTIVITY DRIE FOR VOLUME 3D-SIP AND MEMS

The latest developments in MEMS, Wafer Level Packaging [1] and Active and Passive electronic devices using DRIE have recently allowed the introduction of superior product performances. The future of DRIE technology is now widening thanks to an ever-increasing recognition as an enabling technology. The use of DRIE in high volume applications like mobile phones or automotive sensors is now a reality and manufacturers are always looking for ways to increase capacity by improving throughputs and controlling costs.

Unlike CMOS applications, etching high aspect ratio structures of up to 100:1 [2] with DRIE, suffers from long process times that result in throughputs of only few wafers per hour. The first way to improve throughput is to increase the etching rate with Bosch process [3]. It is obvious that the latest announced etching rates are not sufficient; in this paper, experimental works will be presented showing that 30-35 µm/mn etching rate are achievable. Another way to improve the overall productivity of the DRIE step is to optimize production parameters such as process uniformity, process stability, process yield, system production time, reduction of consumable and scheduled maintenance. Solutions that result in dramatically increasing the wafer throughput and significantly reducing the C.o.O are being presented in this document.

EXPERIMENTAL SET UP

The experiments in this study have been carried out on an Alcatel AMS 200 "I-Productivity" DRIE etching tool, optimized for high volume manufacturing (Fig. 1).

The Alcatel AMS 200 "I-Productivity" is a new generation after the Alcatel "I-Speeder" series and is fitted with an Alcatel patented high-density ICP type plasma source. The source is fixed on top of a diffusion chamber surrounded by a number of permanent magnets. This arrangement allows an optimized process gas delivery as well as high ion density uniformity. The Alcatel AMS 200 "I-Productivity" can be equipped with mechanical or electrostatic wafer clamping solutions. All of the experiments have been performed with patterned silicon wafers of 150 mm diameter size.

The Alcatel DRIE tools are offered with several types of process. The most popular one is the well-known Bosch process based on the use of alternative steps of SF6 and C4F8. The SF6 is used to etch the Si, and the C4F8 to passivate the surfaces and to achieve the anisotropic etch of the Silicon. This alternation of etching and passivation steps results in a waving side wall profile, also commonly called scalloping. With the control of the gas flows and pressures, this scalloping can be significantly reduced, to as low as 14 nm.

SOLUTIONS FOR HIGHER PRODUCTIVITY

2.1. Pushing up Etch Rate to 30-35 µm/mn

In 2002, the "I-Speeder" Project [4] developed with Bosch and PerkinElmer resulted in tools that had the fastest etch rate for Silicon etching in the market. The latest "I-Productivity" project has resulted in further improvement of the etch rate and is now exceeding 30 µm/mn, rate with an excellent etch depth uniformity (Fig. 2).

Fig. 2: Etch rate versus exposed area

2.2. Improving the process YIELD

To achieve a high process yield requires a good depth uniformity as well as good profile uniformity. Such performances can only be obtained with a well-designed process chamber, which leads to an uniform gas phase, uniform plasma, and uniform temperature range across the wafer.

2.2.1. Uniform gas phase

Thanks to its important market share in the high demanding microelectronics business, Alcatel Vacuum Technology has a well recognized position in vacuum expertise. Part of this success is due to the extensive R&D division, and the use of simulation software to achieve the best pump performances possible. One of these 2D software

programs [5] has been used to study the neutral flows at the wafer level for different process regimes on the AMS 200 "I-Productivity" tool. It has also allowed us to optimize the Bosch process in order to achieve the best etch rate and with high etch depth uniformity (Fig. 3a and 3b: Plasma simulation). Optimized simulation now shows excellent gas velocity uniformity all above the wafer surface.

Plasma condition 1: Low uniformity
Fig. 3a: Plasma simulation of the SF6 gas velocity (ms-1) in the chamber showing low uniformity

Plasma condition 2: High uniformity
Fig. 3b: Plasma simulation of the SF6 gas velocity (ms-1) in the chamber showing high uniformity

2.2.2. Uniform plasma

The AMS 200 "I-Productivity" is equipped with the patented high density ICP type plasma source. The source is fixed on top of a diffusion chamber surrounded by permanent magnets. The inherent

non uniformity of ICP plasmas has been dramatically reduced through both chamber dimensioning and magnetic multipolar confinement. Magnet strength and spacing together with inner chamber diameter have been optimized regarding the ion uniformity while providing the maximum pumping speed for processing 8" wafers.

With an 8" wafer, the potential plasma uniformity is better than 5%, which also leads to a comparable etch depth uniformity.

Fig. 4: Plasma potential mapping

2.2.3. Uniform temperature

The surface temperature at the wafer level is a key parameter to achieve good depth and profile uniformity. Furthermore, lots of 3D-SiP applications have a requirement in terms of maximum process temperature allowed on the wafer, due to the type of devices and components on the wafer.

During the Bosch process, after the etch step, which is not sensitive to the temperature, the passivation step shows a linear decrease of the deposition rate proportional to the temperature.

If the edge of the wafer is cooler than the center, then the quantity of polymer deposits at the edge during the C4F8 step will be higher. Since the SF6 step will remove the same quantity of polymer all over the wafer, more polymer will

therefore remain at the edge. The consequence of this phenomena is the appearance of micromasking, leading to a non uniform etch depth and profile across the wafer.

During the ICP DRIE of Silicon in fluorine chemistry, a Si wafer receives energy on its top side and this energy will heat up this surface. On the back side, however, the wafer is cooled by the chuck through the He backside gas pressure. The final surface temperature depends of the ratio deposited on the surface and the amount of energy evacuated by the chuck.

The energy arriving at the wafer surface is the sum of the energies coming from the ion bombardment, the etching chemical reaction and the radiation of the plasma and hot surfaces.

From all the energies arriving at the wafer surface, the most important one is the energy coming from the chemical reaction of the Silicon with the fluorine gas:

Si (s) + 4xF (g)  SiF4 (g) + G0=435 Kcal/mol

This energy (PE) is proportional to the amount of Si removed by time and surface unit:

PE = [Si mol/ (T x Mmol)] x G0

with :
Mmol: The molar mass (28g/mol)
Si mol: quantity of removed Si
T: time
G0 is the chemical reaction

Therefore, PE is directly proportional to the etch rate and the exposed area. That means that a significant increase of the etch rate requires an efficient chuck design to evacuate all the heat generated at the wafer level.

In order to evacuate all this heat and achieve the best uniformity of temperature, Alcatel has designed a "P" type electrostatic chuck (ESC) with an innovative design, that allows the temperature to be adjusted with regard to the wafer patterns. For a given process, the "P" type ESC, gives a uniform temperature of 0.15 degree across the wafer (Fig. 5), with an excellent thermal conductivity.

Fig. 5: Temperature across the wafer with a uniformity of
 0.15 degree for a 1W/cm2 power density

The improved cooling capability of the ESC "P" allows for the development of some new processes that lead to higher etch rates.

2.2.4. Reduced edge exclusion

An another way to increase the process yield is to reduce the edge exclusion, in order to increase the number of properly etched features. The new ESC "P" has been specially designed to avoid any distortion of the plasma sheath at the wafer edge (Fig. 6), and therefore has an edge exclusion not exceeding 3 mm.

Fig. 6: Reduced edge exclusion of 3mm

SOLUTIONS FOR AN INCREASED PRODUCTION TIME

3.1. Clean Free Process Chamber

The C4F8 used for the passivation during the Bosch process creates a polymer that is deposited on all the cold surfaces in the process chamber. The accumulation of this polymer on the chamber wall used to oblige some frequent mechanical cleanings, leading to downtime, and conditioning procedures. In order to avoid any wet cleaning to remove the polymers from the process chamber wall, Alcatel developed a unique patented heated liner [6] (Fig. 7), that allows control the temperature to avoid the deposition of polymers. This unique design avoids an excessive warming up of the outer part of the process chamber, minimizing the electrical consumption.

Fig. 7: Cross section of the patented heated liner

Furthermore, the heated liner maintains a constant plasma condition of the chamber wall, resulting in a Silicon etch rate that is very stable even after multiple plasma hours (Fig. 8).

Fig. 8: Etch stability within 3%

3.2. Reduced C.o.O.

For high volume production, the Cost of Ownership is an important parameter to take into account. More often, The DRIE ICP is used to etch micron or sub-micron features to an etch depth between a few microns up to hundreds of microns. Compared to typical microelectronic processes, the duration of the etch is usually longer even with etch rates ten to hundred times faster. The most efficient way to reduce the C.o.O. is to lower the running costs of the tool.

There are several ways to do this, one of them is to increase the etch rate. Another way is to reduce the C4F8 consumption, a quite expensive gas. As the C4F8 step is more efficient at high pressure, the hardware was modified in order to allow a different pressure for the SF6 and the C4F8. The C4F8 therefore, can be set up at high pressure whatever the value of SF6 pressure. Another way to improve the C.o.O. is to increase the availability of the chamber for process by using the patented heated liner, that reduces the cleaning frequency and duration. The low electrical consumption of the heated liner further adds to the low C.o.O. In addition to the above hardware improvements, the tool design was also significantly modified to reduce the cost and number of spare parts.

BENEFITS FOR A HIGH VOLUME APPPLICATION

4.1. Integration of passive components

All the benefits of the AMS 200 "I-Productivity" DRIE etcher were notably applied to a high volume application for the integration of passive components. Compared to the previous AMS 200 "I-Speeder", the AMS "I-Productivity" improved the etch rate by 43%, and thanks to the reduction of the cleaning frequency the throughput was increased of 83%. The higher range of available process allowed for a decrease of 42% in the consumption of the expensive C4F8 (Fig. 9).

Fig. 9: Benefits of the AMS "I-Productivity"

4.2. Others applications

The AMS 200 "I-Productivity" benefits can also be applied to the high volume MEMS market, such as Silicon microphone or inkjet head applications, but also power devices, passive components, and the emerging 3D applications (interconnection, CMOS Imager…).

Fig. 10: Microtrenches for "Superjunction" applications

Fig. 11: Through the wafer etch for an interconnection application.

Fig. 12: Tapered etch for a CMOS imager application

CONCLUSION

The latest developments and improvements applied to the Alcatel AMS 200 "I-Productivity" result in much higher production performances, thanks to lower etch drift, extended cleaning frequency, limited edge exclusion, higher etch rate, better process stability and higher etch uniformity. It is now possible to offer an unrivaled set of hardware and process solutions, using AMS 200 "I-Productivity" DRIE tools for high volume manufacturing, applied to 3D-SiP and MEMS.


REFERENCES

[1] M. Puech et al. 8th SEMI Microsystem/MEMS Seminar, Dec. 2nd, 2004, pp 143-152.
[2] F. Marty et al. «Advanced Silicon Etching Techniques Based on Deep Reactive Ion Etching for Silicon HARMS and 3D Micro and Nano Structures», ASME European Micro and Nanosystem Conference EMN'04, Oct. 20-21, pp. 25-28.
[3] F. Laermer., A. Schilp, «Method of Anisotropically Etching Si» US patent 5,501,893.
[4] European Commission (Framework V, IST-1999-11261, Semiconductor Equipment Assessement SEA : «I-SPEEDER».
[5] FLUENT® Flow Modeling Software
[6] M. Puech, PCT Patent : WO 2004008477.



AUTHORS
JM.Thevenoud, M.Puech, N.Launay, N.Arnal, P.Godinat, B.Andrieu, JM.Gruffat Alcatel Vacuum Technology Annecy, France

Jean-Marc Thevenoud is Product Manager of the Micromachining Systems Products Group within Alcatel Vacuum Technology France.
Gratuated in 1997 at the University of Strasbourg (France), he joined Alcatel Vacuum Technology in 2000, and spent four years as Technical and Process Manager at Hingham, Massachussetts, in charge of the technical support for the USA and Canada.