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News Article

Epson selects SUSS MicroTec compact mask aligner for wafer level chip packaging

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Seiko Epson Corp. ("Epson has purchased an MA200Compact Mask Aligner from SUSS MicroTec to support their Wafer Level Chip Scale Packaging (W-CSP) production.
Seiko Epson Corp. ("Epson has purchased an MA200Compact Mask Aligner from SUSS MicroTec to support their Wafer Level Chip Scale Packaging (W-CSP) production.

After a careful evaluation of competitive systems Epson decided on SUSS' MA200Compact Aligner because it demonstrated excellent throughput and a submicron overlay and alignment accuracy. In addition, the MA200Compact has been optimized for advanced thick chemically amplified positive tone resists that allow for ninety degree resist profiles. The system that was purchased during the fourth quarter of 2006 will be delivered to Epson's facility in Japan.

"The spirit of creativity and challenge is at the heart of Epson's corporate ethos", comments Akira Makabe, General Manager of Advanced Technology Development Centre at Epson.

"To keep up with the creation of technologies and skills we are constantly seeking for innovative equipment solutions. We chose SUSS MicroTec's MA200Compact, because it combines proven mask aligner technology with highest resolution, submicron overlay accuracy and an excellent wafer yield. The SUSS MA200Compact was able to meet even our most demanding performance criteria."

Rolf Wolf, managing director of SUSS MicroTec' lithography division, noted, " We are pleased that Epson has selected the SUSS MA200Compact to support its wafer level chip scale packaging production. SUSS is excited to be participating in the remarkable progress that is currently being made in Wafer Level Packaging manufacturing."
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