Adoption of SoC platform continues as designs move to 65/45nm process nodes
Sierra Design Automation has launched several new variations to its place and route (P&R) platform addressing critical 45nm design challenges including interconnect resistance variation, complex design rule checks (DRCs) and yield.
The new technologies are built on Sierra's variability-driven physical design. These capabilities are targeted at high-end customers in different market segments such as wireless, handheld, graphics, set-top boxes, networking and processors.
45nm brings with it an increased complexity in routing design rules and design for manufacturability (DFM) requirements for an increased yield. Conventional routing approaches which rely on extensive post-processing to address complex design rules and DFM metrics will no longer work at 45nm. These rules have to be modelled much earlier in the routing flow in order to achieve DRC cleanliness and higher DFM scores.
"NEC Electronics uses specialist design tools and methodologies to design advanced chips in its EMMA platform for digital AV applications such as set top boxes, digital TVs, and DVD recorders," said Masao Hirasawa, General Manager, Digital Consumer LSI Division, NEC Electronics. "We evaluated Sierra's Olympus-SoC router on DRC readiness, routing quality and manufacturing related design closure features for our advanced processes, and are very impressed with the overall quality of results. We look forward to working closely with Sierra to adopt it in our methodology."
"STMicroelectronics continues to design complex ICs for demanding applications such as set-top boxes, secure smart cards and mobile multimedia," said Francois Remond, CAD & design methodology director, Home Entertainment & Displays Group, STMicroelectronics. "Sierra's design-for-variability (DFV) solution is already an integral part of our flow and is proven with multiple tapeouts. With Olympus-SoC's deployment, we have extended the usage all the way to routing for our advanced technologies. We are impressed with the DRC cleanliness, timing and litho-driven routing, and with the overall design closure capabilities."
"Our customers are designing some of the most challenging chips across various application segments in advanced process nodes such as 65nm and 45nm" said Pravin Madhani, president and CEO, Sierra Design Automation, Inc. "Sierra's next generation place & route solution, Olympus-SoC, addresses the physical design and manufacturing challenges at these nodes comprehensively. Transition to 65nm and 45nm is a disruptive event and we are seeing widespread adoption of the Sierra solution at these nodes. "
