TSMC endorses ATopTech's Tools for 16nm FinFETs
ATopTech has announced that Aprisa and Apogee, the company's place and route solution, have been certified by TSMC for 16nm FinFET v0.1 design enablement.
ATopTech is a developer of physical design solutions that address the challenges of designing integrated circuits (ICs).
TSMC's 16nm FinFET technology offers improved design performance, lower overall power, and smaller area.
Aprisa and Apogee were certified in October 2012 by TSMC for 20nm design enablement with double patterning technology (DPT) routing rule support for TSMC's 20nm reference flow.
Aprisa's colour-aware DPT routing technology uses a correct-by-construction approach that guarantees no missing DPT violations at signoff while achieving excellent routability and router runtime.
Aprisa and Apogee has subsequently gone through a rigorous 16nm FinFET certification process that includes signoff correlation checking of design rule checking (DRC), layout versus schematic (LVS), and formal verification to fulfil new process requirements. These include new design rules for P-80 layers, 16nm FinFET transistor-related placement rules and DFM requirements.
"ATopTech's technologies were purposed for just such advanced process technologies as TSMC 16nm FinFET," says Jue-Hsien Chern, CEO of ATopTech. "This close collaboration with TSMC further enables our joint customers to take full advantage of the TSMC advanced technology for better product competitiveness."
"ATopTech's certification demonstrates significant ecosystem progress as we prepare our joint customers for 16nm FinFET design," adds Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division.
