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Meeting Next-Generation Advanced Packaging Geometries Through Material Advancements

The boom in the mobile market with increasing demands for smaller geometries has created the need for novel and innovative chemistries to overcome the limitations of existing materials. Jianwei Dong, Wataru Tachikawa, Richard Chen and Joon-Seok Oh at Dow Electronic Materials discuss material advancements and how they meet the needs of next-generation wafer-level, 2.5D and 3D packaging technologies.

The exploding mobile market is driving feature requirements for next-generation semiconductor devices to increasingly smaller geometries. As a result, there is increased risk of wafer stress due to more delicate features, thinner wafers to handle, and in the case of 3D IC technologies, higher density through silicon vias (TSVs) and the need to accommodate microbump structures. Equipment and processes can only go so far with existing material sets initially developed for the last generation of packages before they hit process limitations. The task has fallen largely on the shoulders of material science to tackle these limitations with novel and innovative chemistries. 

Fortunately, as the entire semiconductor packaging ecosystem has entered a new age of cooperation and transparency, collaboration with R&D centers and partnerships with equipment suppliers have resulted in significant developments across the spectrum of advanced packaging materials to meet these new challenges. This article will present a number of recent technology breakthroughs including compatibility of metallurgies for tin silver (SnAg) capped copper (Cu) pillars; advancements in temporary bond/debond adhesives that allow for clean debond from active device wafers at room temperature; pre-applied underfill for die stacking that addresses the fine pitches required for stacking logic system-on-chips (SoCs) with TSVs; and low stress, high performance dielectrics that address increased stress and wafer bow resulting from thinner substrates. These material advancements began with either new material formulations or proven materials that have been optimized to address the emerging requirements of next-generation devices. 

SnAg-Capped Cu Pillars
With mobile device manufacturers clamoring for higher density, fine-pitch ICs, a trend to replace conventional flip chip solder bumps with Cu pillar bumps capped with SnAg solder has emerged. This is because SnAg capped Cu pillars enable the higher density interconnects and lower profiles needed for emerging 2.5D interposer and 3D packaging applications. Devices that have made the transition to SnAg capped Cu pillars include high-end graphics processors, FPGAs, power amplifiers, MEMS and HB-LEDs. 

In particular, silicon interposers and fine-pitch Cu pillar micro-bumps represent the two technologies that have come to define a 2.5D packaging approach. Cu pillars provide the short, low inductance, efficient interconnections between ICs in vertical stacks as well as between an IC and the silicon interposer. Capping Cu pillars with SnAg allows for improved reflow with the silicon interposer, achieving <40µm pitches. Together, micro-bumps and silicon interposers provide a high-speed and high-bandwidth communication highway for side-by-side die (and stack) placement.1 

When selecting materials that will result in high-yield, reliable electroplated Cu pillar and Cu µpillar capped structures, it is important to consider the interface between metal layers, particularly as Cu pillar cap diameters shrink to µpillar dimensions (<30µm diameter). Additionally, interfacial properties and intermetallic compounds (IMCs) must be understood and controlled. The plating chemistry has significant influence on the compatibility of each layer, as well as control of IMC-growth, micro-void formation and overall stack reliability. 

In designing chemistries, the compatibility of the Cu and solder materials is of critical importance. This compatibility is evidenced by such characteristics as a smooth, continuous IMC layer formed after reflow of Cu pillar and Cu µpillar with SnAg solder caps (Figure 1). The dominant IMC formed is Cu6Sn5 between the Cu and SnAg interface after reflow. IMCs make up a significant fraction of the SnAg cap for Cu µpillar bump. Additionally, no interfacial voiding should be observed after reflow.

Figure 1: Left, Cu µpillar with SnAg cap as plated. Right, Cu µpillar with SnAg cap post reflow. 

Further, industry needs for higher throughput, smaller, finer pitch features and low cost of ownership (COO), in addition to requirements for flatter pillars with smooth surface and good uniformity, is driving further development work on next-generation Cu pillar and SnAg chemistries. 

The most recently developed formulations have satisfied all key design criteria including highly uniform Cu pillars (within die (WID) < 5%); a flat pillar profile (total indicated runout (TIR) < 5%); smooth surface morphology; and compatibility with SnAg capping (Table 1).

Deposit Property (Relative)

Legacy Formulation

Cu Pillar

Formulation A

Cu Pillar


Surface profile

Domed (TIR>0)

Flat (TIR~0)

Surface morphology



Organic incorporation in bulk Cu

Relatively low (<20ppm total)

Relatively low

(<20ppm total)

Compatibility with SnAg capping



Table 1: Comparison data of a commercially available product and a new Cu Pillar formulation.

Additionally, a compatible SnAg counterpart to the Cu pillar chemistry has been developed, resulting in a formulation that demonstrates high speed plating (>3µm/min); highly uniform SnAg deposits; (WID <±5% for challenging fine-pitch die designs); macro and micro void-free performance (X-ray); smoother surface morphology (as-plated and post-reflow) and a smoother, void-free interface with Cu pillar compared with its predecessors. Overall, this material exhibits the widest process window with the most robust process flexibility and a competitive COO. 

Temporary Bond/Debond
In 3D IC development, the temporary bond and debond step has provided ongoing obstacles and continues to be considered a roadblock to commercialization. Materials must meet temperature stability and chemical resistance requirements due to the various process steps that a bonded wafer pair undergoes -- from the time of application to the process wafer, through the backside thinning and processing, debonding and cleaning. 

The adhesive used to create a temporary bond should have certain attributes to be considered practical. For example, the adhesive has to survive several processes that will inflict environmental extremes. The bond has to be strong enough to support the wafer through the thinning process, but easily debonded when needed without damage to the wafer or the electronic devices. The debonding must be gentle since the wafer is so fragile and any remaining residue needs to be easily removed.2

While many materials on the market have achieved many of these attributes, the gating technical issue has been with the debonding step. One solution that has recently been developed is based on a well-established permanent bonding adhesive. This benzocyclobutene (BCB) material offers inherently attractive material properties such as high thermal stability (withstanding temperatures up to 300°C), high chemical resistance and low temperature curing. It has been successfully modified to make it easily releasable from various surfaces, allowing it to be used effectively as a temporary bonding adhesive. 

Clean debonding is critical, and this one requires no additional process steps for removal from the active die surface, such as laser/UV ashing or solvent soaks. Rather, an adhesion promoter is spin-coated onto the carrier wafer so that when it is debonded using mechanical lift-off at room temperature, the adhesive goes with the carrier and leaves the device wafer free of adhesive material (Figure 3). In the event of bumped wafers, a solvent rinse may be required to remove any minor residue. 

Another advantage of the modified BCB material is that while it withstands high temperatures (>300oC/1 hr), it bonds at low temperatures, which eliminates bonder/heater time and increases wafer throughput. Final cure is then performed in a batch oven process outside the bonder with no alignment shift, for increased throughput and reduced COO.


Figure 2: Even dense, C4-bumped wafers debond cleanly: SnAg solder bumps after debonding (left), BCB-based temporary bonding adhesive film after debonding (right, below)

Pre Applied Underfill 
Underfilling 3D IC stacks is critical to help control TSV-induced stress and also to help control warpage of these ultra-thin stacks caused by CTE mismatch between the device and its substrate. In fact, thermal modeling and simulation studies show that underfill, substrate and mold compound thermal strains play important roles in the warpage evolution.3

After backside processing, thin devices must be assembled into stacked-die structures. Current underfill technologies required for assembly have issues with voiding and have been known to result in filler entrapment during bonding. Additionally, there have been issues with bleed and creep of underfill around the die, particularly with today’s finer pitch geometries. 

Alternatively, pre-applied underfills allow for simultaneous electrical and adhesive die bonding. One such material has performed well when applied as a wafer-level underfill for bonding Cu pillars with 25µm diameter and 50µm pitch on thinned die. 

When applying via vacuum lamination to 300mm wafers, the result is good uniformity and thickness. It also addresses the fine pitches required for stacking logic SoCs with TSVs; an application where capillary underfills fall short. Test vehicles have demonstrated 100 percent electrical joining after thermocompression bonding (Figure 3).

Figure 3: 100 percent electrical joining of 1600 solder joints per daisy chain

Low Stress High Performance Dielectrics
As previously mentioned, increased stress and wafer bow is also an issue due to the thinner substrates required for vertical integration in TSV and 3D packages. In addition to underfill materials and molding compounds, cured dielectric materials also contribute to the condition. Recent developments extending the thermal, electrical and chemical stability of BCB-based materials have resulted in a lower residual stress prototype of a photodielectric that is currently used in high-volume manufacturing. 

The new polymer is modified to allow compatibility with conventional tetramethyl ammonium hydroxide (TMAH)-based developers, vs. the traditional solvent-based BCB photodielectric. The new aqueous-developable BCB photodielectric material can easily produce patterned features to 5 µm and below, with aspect ratios of 2:1. In addition to lower COO and the aforementioned lower residual stress, this photodielectric material also exhibits desirable properties such as low-temperature cure, high thermal stability with low outgassing to withstand SnAg reflow temperatures and excellent mechanical properties needed to survive integration and meet the needs for improved elongation. 

Figure 4: 70º tilt cross sections SEM of XP120201 depicting 5 µm, 1:2 contact holes after develop (left) and after soft cure (right). 

Materials suppliers increasingly find themselves in the role of developing solutions to overcome known challenges or limitations of existing processes and equipment. The surest and most efficient approach to address the emerging requirements of next-generation devices is to innovate new technologies that leverage and optimize proven materials when possible. Therefore, combining the known performance of existing material sets with the enhanced capabilities of new chemistries is ideal for accelerating the transition to future manufacturing nodes. As a result, a full suite of compatible chemistries is now ready to meet the needs of next-generation wafer-level, 2.5D and 3D packaging technologies. 


1. D. Patterson, “2.5/3D Packaging Enablement through Copper Pillar Technology", Chip Scale Review, July/Aug 2012, p20

2. J. A. Sharpe, M. B. Jordan, S. L. Burkett, and M. E. Barkey, “Analyzing the Behavior and Shear Strength of Common Adhesives used in Temporary Wafer Bonding" Proc., 2013 Electronic Components Technologies Conference, pp 94-95

3. K. Karaminal, “A Comparative Simulation Study of 3D Through Silicon Stack Assembly Processes", Proc. 2013 Electronics Components Technology Conference p. 1


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