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Oxide-free Room-temperature Wafer Bonding For Fabrication Of Engineered Substrates

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Christoph Flötgen, Nasser Razek, Viorel Dragoi, Thomas Uhrmann, Markus Wimplinger and Paul Lindner of EV Group look at a novel bonding method which enables the generation of oxide-free covalent bonds at room-temperature, which allows a multitude of crystalline or poly crystalline semiconductors to be bonded permanently. 
Silicon is the semiconductor material of choice when it comes to optimized manufacturing processes, high-yield fab environments, as well as lowest possible cost. In terms of performance, several other elemental or compound semiconductors could easily outpace silicon from a material science point of view. Innovations in process technologies—such as lithographic scaling—extended silicon device capabilities for decades, where industry followed the concept: if it can be done in silicon, it will be done in silicon. Nevertheless, future devices are expected to reach the inherent material limits of silicon in terms of electron mobility, carrier density or, most importantly, missing optical properties. As a consequence, integration of compound semiconductor materials on silicon rapidly gains importance.  

Several methods for the manufacturing of such engineered substrates of compound semiconductor materials on silicon are under evaluation at present. One solution would be epitaxy of compound semiconductors directly on silicon. Yet, high growth temperatures, mismatch in lattice constants as well as mismatch in coefficient of thermal expansion (CTE) introduce major difficulties. As a result, grown films show a high density of crystal dislocation, which deteriorates device performance later on. 

The most promising solution for on-silicon integration of compound semiconductors is wafer bonding, where compound semiconductors can be grown on appropriate substrates and subsequently transferred to silicon for further processing. Oxide-to-oxide fusion bonding has been the standard process since its use for more than a decade for the manufacturing of layered substrates or engineered substrates, such as silicon-on-insulator (SOI) wafers. Oxide layers at the interface enable this type of bonding, in turn leading to a non-conductive interface between both bonded substrates. However, several applications in power devices, stacked solar cells, micro electro mechanical systems (MEMS) and engineered substrates, to name only a few examples, can benefit by employing conductive bonding interfaces for improved device performance. 

The following novel bonding method enables the generation of oxide-free covalent bonds at room-temperature. In this way, a multitude of crystalline or poly crystalline semiconductors as well as other materials such as metals and ceramics can be bonded permanently. Removal of inherent or protecting oxide layers from the surface results in conductive bond interfaces. In addition, a very low bonding temperature enables the combination of materials with highly different CTEs.

Room-temperature covalent bond process flow  
Oxide-free bonding has been carried out on the EVG580 ComBond as shown in Figure 1. Wafers to be bonded are loaded in cassettes via load ports, before being introduced to the high-vacuum mainframe. The wafers are first processed in sequence in the CAM module (ComBond Activation Module) for surface preparation and oxide removal. This dry oxide removal step is discussed in further detail in the following paragraph. Keeping the wafers in a high-vacuum environment after surface removal prevents re-oxidization of the first monolayer of the semiconductor surface while the wafer is undergoing further processing in the bonding cluster system. Since the surface preparation step takes only a few minutes for each wafer, re-oxidation can be prevented for several substrate and activation conditions. 


Figure 1: EVG580 ComBond high-vacuum cluster tool for oxide-free low-temperature wafer bonding.

In-situ oxide removal 
The cornerstone for oxide-free bonding lies within the preparation of both substrates, paired with prevention of re-oxidation prior to bonding. Existing opportunities for the removal of oxides are either by wet chemical etching or dry etching. In CMOS processing, wet chemical etching using hydrofluoric acid is commonly employed for removing thin silicon oxides while also showing a high selectivity to underlying materials. In contrast, other semiconductor oxides and metal oxides are difficult to etch or control. For engineered substrates, the combination of different substrates and integration with compound semiconductors significantly adds to chemical etching complexity. Hence, several bond materials introduce material supply, shelf life and waste management issues. Probably the biggest issue with wet chemical etching is the potential for re-oxidation prior to bonding, as wet etching is accomplished under ambient (non-vacuum) conditions.

Dry etching, on the other hand, offers several advantages for oxide removal prior to wafer bonding. Any oxide layer can be removed effectively by directing energized particles at the substrate surface.  The impact of particles on the substrate surface introduces energy that leads to amorphous layer formation below the sample surface. In order to prevent re-oxidation of the surface, substrates are etched and handled in a high-vacuum environment. 

Surface control during oxide removal
Effective oxide removal while simultaneously minimizing damage of the underlying substrate material is essential to a successful bonding process. In addition, low surface roughness has to be maintained to allow for uniform contact at nanoscale dimensions during bonding. Experiments have been carried out with 200-mm silicon wafers, which have been analyzed before and after surface preparation using atomic force microscopy (AFM). Figure 2 shows a representative AFM measurement of the surface after treatment. A quadratic mean micro roughness of less than 0.2 nm is found to be a characteristic value for all conducted measurements after oxide removal. It is worth noting that wafers show either no change or a slight improvement in micro roughness values after treatment in the CAM module. 


Figure 2: Representative Atomic Force Microscopy (AFM) measurement of a 200-mm silicon wafer after oxide removal.
 
Etching of oxides with energized particles often results in back-sputtering effects, leaving particles on the wafer surface. As a result, such particles create voids at the interface between bonded wafers. Typically, wafer bonds are characterized using scanning acoustic microscopy (SAM) where the wafer pair is immersed in water and ultrasonic reflection spectra are analysed. 

Acoustic reflections are generated from particles, while ultrasonic pulses can travel undisturbed if the bond is closed (meaning the bond yield is good). One characteristic bond is shown in Figure 3, where no voiding areas are visible. The high bond yield essentially shows that no particles are re-deposited to the wafer during preparation. 


Figure 3: Surface Acoustic Microscopy measurement of 200mm silicon to silicon bonded wafer pair. The bond interface shows no entrapments or voids, which would be visible with a white contrast in this measurement.

Analysis of the bond interface
Besides the wafer surface, the bond interface should also be further analysed. On the one hand, no impurities should be introduced into the bonding interface. Impurities at the bond interface can impact the performance of any subsequently manufactured device. Mobile ion contamination is especially critical, where the equipment showed concentrations of less than 5*1010 atoms/cm² for all elements using VPD-ICPMS measurements. On the other hand, the amorphous region at the interface has to be free of re-oxidation. 

Figure 4 shows a high resolution transmission electron microscopy (HR-TEM) image of the bond interface of two silicon wafers. The well-defined transition between crystalline bulk region and the amorphous bond interface reveals an amorphous layer thickness of about 2.6 nm. In conjunction with experimental results, Monte-Carlo simulations (SRIM) have been carried out to fit the experimental results with theoretical predictions of silicon atom displacement [1]. 


Figure 4: High resolution TEM image of the bond interface, showing amorphous layer thickness of 2.4 nm. The superposed simulation using SRIM correlates well with the experimental data, where the solid line corresponds to Si-atom replacements and the dashed line refers to vacancy defects.

Simulation is superposed to the HR-TEM image in Figure 4 and proves a strong correlation to the experimental data. The simulation resembles two different defect types, namely replacement (full line) and vacancy displacements (dotted line). Clearly, the interface region is dominated by vacancy displacements as most of the energy from particles during oxide removal is absorbed in the top layer. 
 
If re-oxidation is present, the contrast in HR-TEM image between oxygen and silicon atoms in the amorphous region would be too low to measure it. Therefore, energy-dispersive X-ray spectroscopy (EDXS) has been chosen to measure for re-oxidation since EDXS is highly elemental sensitive and can detect any sign of oxidation at the interface. Three different measurement spots have been chosen in order to correlate results from the interface to the silicon bulk region of the bonded wafers. Since the oxide should be completely removed prior to bonding, only silicon atoms should be at the interface. Figure 5 shows the results of these measurements. As shown, the EDX spectra taken in the bulk silicon regions, marked with 1 and 3, are the same as the analysis from the interface (2), concluding that an oxide-free bonding has been successful. 


Figure 5: EDX spectra correlated to different regions of the sample. Corresponding oxygen and carbon signals are the same for all measurement areas 1 to 3, clearly correlating to sample preparation for HR-TEM and reveal an oxide free bonding interface.
 
Conclusion and outlook
In summary, several market applications demand room-temperature bonding of substrates with very different material properties, mainly for the production of engineered substrates, power devices, stacked solar cells and MEMS devices. The oxide-free bonding technique presented in this study enables the combination of materials with dissimilar properties in order to manufacture new devices for many of these applications. One example is the stacking of different solar cells, such as gallium arsenide (GaAs)-based cells to germanium (Ge) cells through bonding instead of traditional epitaxial growth processes, which are difficult to implement and control due to the structural and temperature restrictions of the different semiconductor materials. 

Several other engineered substrate applications also benefit from room-temperature bonding, including but not limited to GaAs on silicon, gallium nitride (GaN) on silicon, silicon carbide (SiC) on silicon, and lithium tantalate (LiTaO3) on silicon. Since the bonding technique presented here minimizes mobile ion and particle contamination through surface treatment and oxide removal prior to the bonding step, it can be integrated into standard MEMS or semiconductor process flows. 

Low impact to underlying substrate materials through the highly selective surface preparation process integrated in the bonding system combined with room-temperature bonding enables near-limitless material combinations of semiconductors, metals and ceramics. 


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