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Thursday 1st April 2004
Cleaning after the chemical mechanical planarisation (CMP) process has traditionally been of the spin-rinse-dry (SRD) variety. These processes often leave particles in the form of water marks that could create killer defects in 65nm processes. Applied Material’s new Desica vapour-dry module is designed to eliminate SRD-related water marks on low-k metal interconnect patterned wafers.
Thursday 1st April 2004
Cleaning residues from processing is a key step in semiconductor production. New transistor gate materials are due in the near future with the use of High-K Gate insulationand metal rather than polysilicon gate electrodes. Researchers from IMEC and Spin Processor tool producer SEZ consider the implications of such new materials for cleaning.
Monday 29th March 2004
When is the best time to institute ‘equipment lifecycle management’ and enlist the aid of an outside asset management organisation? “Right now,” says Trey Brown, general manager, GE Global Electronics Solutions
Monday 29th March 2004
The annual SEMI Industry Strategy Symposium was held in Paris in February. With the longest downturn for the industry the attendees were looking for positive feedback. David Ridsdale was there to see if expectations were met.
Monday 29th March 2004
Semicon Europa lands in Munich once again in April. Changes in the industry has seen the traditional trade show lose its relevance to the European community and the European SEMI team have responded to the concerns raised by their members. David Ridsdale spoke to Walter Roessger, President of European SEMI about the changes implemented for this year’s show and why they were implemented.
Monday 1st March 2004
Microelectronics manufacturing has always relied on the lithographic process to ensure Gordon Moore's observation remains accurate. Historically the transition stages for advanced lithography have been a carefully laid out procedure. Economic realities have disturbed this natural conservative order and the industry now looks to a re-imagining of traditional processes to move to the next technology node. Alan Stein of Rohm and Haas Electronic Materials, looks at new materials that will help extend 193nm lithography, maybe to the 45nm node...
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Monday 1st March 2004
The last few Semicon Europa events saw the European SEMI office receive complaints that the original trade show format was no longer relevant to a changing industry. To the credit of the European SEMI team they have responded and Europe’s premier semiconductor show continues to go through changes to make it a more relevant entity to all participants. Vincent Dubois of European SEMI has provided Eurosemi with an outline of what to expect at the show...
Monday 1st March 2004
Product-focused chip firms recognise the need to continually bring compelling, reliable new products to market in order to maintain competitive advantage. Companies across a wide range of industries are adopting product lifecycle strategies and solutions to speed development and introduction of new products, while reducing risks and costs associated with operation of a global value chain of customers, employees, partners and suppliers, writes Jaap Smit of MatrixOne...
Monday 1st March 2004
New mass imaging process technology has opened the possibility of printing at the wafer level and even on singulated substrates. Ricky Bennett, Applied Product Development manager at DEK, reports on collaboration with AMD...
Monday 1st March 2004
Alternating phase shift reticles are one proposed solution for printing features required at the 90nm and 65nm nodes using 193nm lithography. A key enabler to is defect inspection so as to guarantee that defect free reticles are delivered to wafer fab production. A joint team from KLA-Tencor and International SEMATECH report several of the challenges in the design and manufacture of a programmed defect test reticle for this technology...
Sunday 1st February 2004
Integrated circuit features continue to race downwards. As physical limitations of silicon are approached, lithography techniques become increasingly difficult. More than ever before, etching binary chromium (Cr) masks is the resolution-limiting step within the manufacturing process of advanced masks sets, write Michael D Archuletta, Dr Chris Constantine and Dr Dave Johnson of Unaxis Semiconductors.
Sunday 1st February 2004
Previous generations of devices placed technical challenges on sectors apart from bond testing. With industrial bonding at 50µm becoming common place, this is no longer the case, writes Robert Sykes of Dage Precision Industries. His company launched the Series 5000 bond tester at SEMICON West this year aimed at just this market for ultra fine pitch products.
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Sunday 1st February 2004
Reducing k values of dielectrics below 2.5 presents major semiconductor process challenges. The need to introduce pores into low-k materials creates serious process weakness. Keith Buchanan of Trikon Technologies describes some of the factors involved and possible solutions for his company's Orion low-k dielectric.
Friday 16th January 2004
A wide variety of inorganic and organic films that have high temperature stability have been proposed for both spin-on and chemical vapour deposition (CVD) low-k and ultra-low-k (ULK) applications [1]. Thus far, the only materials capable of successful integration in copper dual damascene processing have been inorganic films with k values greater than 3.0. Sub-90nm generations of IC manufacture need effective k values substantially lower than this.
Friday 16th January 2004
The annual MEDEA+ conference was held in Berlin last month. With the worst downturn in microelectronics history limping to a close, the mood at the event was one of European unity. Unified in the realisation that the European microelectronics industry was heading for potential financing difficulty. David Ridsdale was there to hear the feedback from Europe’s foremost research consortia.
Friday 16th January 2004
Every year European Semiconductor presents a Start Up Award recognising excellence in a European semiconductor company that has been in existence for less than five years. David Ridsdale went to visit the 2003 winner, Lotus Systems in lush Southern Germany.
Friday 16th January 2004
Mask making is not an easy business these days. Semico Research describes some findings from its report "Mask Making: Rising Costs, Changing Business Models, New Technologies"
Saturday 1st November 2003
It is getting harder to stay at the forefront of the semiconductor game. Even the biggest companies now have to collaborate in some form. IMEC has just launched an initiative to put itself at the centre of this collaboration for 45nm and beyond. Mike Cooke reports from IMEC's Annual Research Review Meeting...
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Saturday 1st November 2003
Costs are pushing more and more functions onto a single chip. In the RF world, this manifests itself as more and more digital and mixed signal components showing up on what were traditionally RFICs. Edwin Lowery of Agilent Technologies discusses how the different RF and mixed-signal test traditions should be merged...
Saturday 1st November 2003
Traditional high downforce (>2.0psi, 14kPa) chemical mechanical planarisation (CMP) processes face challenges when used to polish copper with low-k films in damascene interconnect structures. Peeling/delamination occurs in low-k films with weak mechanical strength due to the relatively high shear force. Additional problems include stress fractures and particle damage. Researchers from Applied Materials' CMP group describe a low-shear, low-downforce (
Saturday 1st November 2003
Getting chemical mechanical planarisation (CMP) right is one of the key factors in successful back-end of line processing. James J McAneny and John H Welty of Logitech describe how a small scale CMP system can be used in an R&D environment to test new processes...
Saturday 1st November 2003
Photoresists are the key chemical component of the microrelief patterning used in semiconductor processing. But what if they could do more? Researchers from ELCOTEQ of Estonia and the St Petersburg State Technological Institute in Russia show how photoresists could be used to deposit dielectrics, deliver diffusion dopants and create colour filters for digital imaging...
Thursday 16th October 2003
WHILE BALL BONDING IS THE MOST ECONOMICAL METHOD OF WIRING CHIPS TO PACKAGES IT IS LIMITED IN APPLICATION TO AREAS WHERE HIGH TEMPERATURES ARE NOT A PROBLEM. THE COOLER ULTRASONIC WEDGE-WEDGE WELDING TECHNIQUE HAS TO NOW SUFFERED FROM LOWER THROUGHPUTS. BOND TOOL COMPANY HESSE & KNIPPS HOPES TO CHANGE THIS WITH ITS NEW BONDJET 815 To Read More Click Here
Wednesday 1st October 2003
Digital image correlation can be used to measure deformations in IC package structures before the development of actual defects. Optical Metrology Innovations (OMI) based in Cork, Ireland, has developed its OMISTRAIN system based on the technology...

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