CEA-Leti advances alternative computing architectures.
Two recent developments from CEA-Leti highlight the breadth of innovation occurring beyond conventional CMOS scaling. The first demonstrates a hybrid memristor-spintronic Ising machine capable of solving combinatorial optimisation problems using intrinsic annealing mechanisms. The second expands collaboration with quantum start-up Quobly to accelerate the development of scalable silicon spin-qubit technologies through access to Europe’s FAMES pilot line infrastructure.
By CEA-Leti
As performance gains from conventional processor scaling continue to slow, increasing attention is being focused on domain-specific computing architectures capable of delivering significant improvements in performance-per-watt for targeted workloads. CEA-Leti’s latest research activities illustrate two distinct but complementary approaches to this challenge: hardware-native optimisation accelerators based on emerging nanoelectronic devices, and silicon-based quantum computing platforms that leverage established semiconductor manufacturing ecosystems.
Recent announcements from the Grenoble research institute showcase advances in both fields. Researchers from CEA-Leti, Spintec and C2N have demonstrated a hybrid nanoelectronic Ising machine that combines hafnium-oxide memristors and stochastic magnetic tunnel junctions (SMTJs) within a unified optimisation architecture. At the same time, CEA-Leti and quantum computing company Quobly have strengthened their long-standing collaboration around silicon spin-qubit technologies, with Quobly gaining access to the FAMES Pilot Line to evaluate future process technologies.
Together, the developments underscore the growing importance of heterogeneous computing approaches as the industry seeks alternatives to traditional von Neumann architectures.
Hardware-native optimisation
Combinatorial optimisation remains one of the most computationally intensive classes of workloads in both scientific and industrial computing. Applications ranging from logistics optimisation and power-grid management to EDA workflows and data-centre resource scheduling routinely involve solution spaces that grow exponentially with problem size.
The hybrid Ising machine reported in Nature Communications addresses these challenges through a hardware implementation of local-search optimisation functions. Rather than executing optimisation algorithms through a sequence of software instructions, the architecture exploits the intrinsic physical behaviour of nanoscale devices to perform key computational operations directly within the hardware fabric.
The system combines hafnium-oxide memristors arranged in crossbar structures with stochastic magnetic tunnel junctions whose thermally driven switching behaviour introduces controlled probabilistic dynamics into the optimisation process. Memristors encode the coupling coefficients that define the optimisation problem, while SMTJs represent the binary state variables whose evolution drives the search towards lower-energy solutions.
A notable contribution of the work is the demonstration of an intrinsic annealing mechanism. Annealing schedules are fundamental to Ising-based optimisation because they govern the transition from exploratory to convergent system behaviour. In many existing implementations, this requires supervisory circuitry and significant control overhead. In the CEA-Leti architecture, however, the coupling between the memristor network and SMTJs enables annealing behaviour to emerge naturally through adjustment of the memristor read voltage, substantially reducing control complexity.
Toward scalable ising accelerators
Experimental validation was performed on benchmark graph optimisation problems, including weighted MAX-CUT and graph-colouring tasks. The prototype consistently identified optimal solutions for instances comprising 24 vertices in weighted MAX-CUT and 10 vertices in three-colour graph-colouring configurations.
While the present implementation relies on sequential updates and external feedback loops, the underlying architecture is designed with large-scale integration in mind. Future implementations could exploit direct coupling between crossbar arrays and spintronic devices, eliminating analogue-to-digital conversion bottlenecks and enabling highly parallel operation.
From a semiconductor integration perspective, the approach is particularly attractive because both ReRAM-based memristors and magnetic tunnel junctions are compatible with CMOS back-end-of-line processes. This creates potential pathways towards monolithic three-dimensional integration, a key requirement for practical deployment of specialised optimisation accelerators.
For high-performance computing and data-centre applications, such architectures could ultimately provide low-power acceleration of scheduling, placement, routing and resource-allocation workloads that increasingly impact operational efficiency.
Silicon quantum computing moves toward industrialisation
Alongside its work in emerging optimisation architectures, CEA-Leti is continuing to advance Europe’s silicon quantum computing ecosystem through its collaboration with Quobly.
Unlike superconducting and trapped-ion quantum computing approaches, silicon spin-qubit technologies seek to leverage mature CMOS manufacturing processes and existing 300 mm semiconductor production infrastructure. This compatibility is widely regarded as one of the most promising routes towards achieving the device densities and manufacturing scalability required for fault-tolerant quantum processors.
Quobly’s QSOI® architecture combines silicon spin qubits with FD-SOI process technology and is being industrialised in partnership with STMicroelectronics. Through access to the FAMES Pilot Line, Quobly will now be able to investigate advanced process modules, lithographic approaches and fabrication flows that may support future generations of quantum processors.
The collaboration builds upon more than 15 years of joint research between CEA-Leti and CNRS, including the demonstration of an industrially fabricated silicon spin qubit on a 300 mm FD-SOI wafer in 2016. The current focus is centred on developing the integration technologies, control architectures and manufacturing methodologies needed to support large-scale quantum processor implementations.
Taken together, the two announcements illustrate CEA-Leti’s strategy of pursuing multiple post-CMOS computing pathways simultaneously. While the hybrid Ising machine addresses near-term opportunities for accelerating optimisation workloads through specialised hardware, the Quobly collaboration focuses on the longer-term objective of scalable quantum computing built on established semiconductor manufacturing foundations.
For the semiconductor industry, both initiatives highlight a broader shift towards heterogeneous computing architectures in which emerging device technologies, advanced integration schemes and application-specific accelerators are expected to play an increasingly important role alongside conventional CPUs and GPUs. As AI, HPC and data-centre workloads continue to grow in scale and complexity, such specialised platforms may become critical components of future computing infrastructures
