Onsemi takes power integration to the wafer

With dies embedded directly into a silicon wafer, onsemi is targeting higher density, better thermal performance and tighter integration in AI and electric vehicle applications.

By Rebecca Pool, Technology Editor

Targeting the soaring power demands of AI infrastructure, onsemi has developed a silicon-wafer-based architecture that embeds multiple power and control dies within a single power module. The Embedded Power Platform promises three to five times higher power density than conventional approaches, depending on the application, while simplifying system-level integration.

“For decades, the semiconductor and the package have been treated as separate technologies. The Embedded Power Platform changes that by making the silicon itself part of the system architecture,” highlights Hassane El-Khoury, President and CEO of onsemi. “The platform brings together advanced semiconductor technologies, manufacturing and system-level optimization into a common architecture that can evolve alongside future innovations.”

In one of its EPP-based solid-state circuit-breaker designs for an AI rack, onsemi claims the design was around 50% smaller and 20% cooler than existing designs.

According to the firm, by reducing packaging and using the full EPP footprint to conduct heat, multiple dies can be packed closer together - so the platform can support more compact power systems, improve thermal management and enable greater power density in AI infrastructure.

Meanwhile, in electric vehicle applications, the platform is said to provide up to four times higher power density and 15% lower power losses compared to conventional approaches, delivering smaller, lighter and more efficient inverter designs.

“This approach will redefine how power systems are built and create a new foundation for AI infrastructure, electrification and automation,” says El-Khoury.

Meet the platform
As AI, automotive and industrial systems demand more power in less space, designers face mounting pressure to improve efficiency while managing heat, size and cost. The EPP is a silicon wafer embedded power module designed to optimise electrical, mechanical and thermal performance within a single architecture. Here, individual silicon, silicon carbide and gallium nitride dies can be directly embedded into a 300 mm (12 inch) silicon wafer. These dies can be connected through wafer-level redistribution layers – this interconnect structure is fabricated using wafer-level semiconductor processes.

Importantly, the wafer is now functioning as the basis of the power module rather than a substrate from which the active devices are fabricated. According to onsemi, the design also integrates electrical, mechanical and thermal considerations from the outset, which transforms the package from passive housing into an ‘active contributor to system performance’.

Allyson Fairchild, Automotive Field Applications Engineer and Strategic Project Lead - Corporate Strategy and Advanced Projects at onsemi, emphasises how the platform supports myriad applications and different semiconductor materials, and is scalable across multiple power levels. “We can embed heterogeneous dies within the package... that could be the major power devices - MOSFETs and JFETs,” she says. “But we can also embed controls, drivers and other supporting power devices – this enables really tight electrical coupling and we’re reducing complexity at the system level.”

“This allows us to get the most out of these products,” she adds. “Customers are getting a product that is easier to integrate into, say, their data centre rack or any other application.”

Onsemi has been working on designs that use half bridges for traction applications as well as multiple FETs connected in parallel for lower on-resistance, and dies connected to controller dies to minimise the loop inductance. “Whatever the application requires we can embed the dies and connect them into the [necessary] configuration,” points out Fairchild. “This will also evolve with semiconductor innovation, and having this technology-agnostic platform will allow us to take the technology far into the future.”

“The sky’s the limit here – we really have the opportunity to be inventive,” she says.

Instead of relying on conventional wire bonds and other assembly-level connections, the platform uses wafer-level metallization to form precise copper interconnects – an approach that reduces parasitic inductance, improves device control and enables high switching frequencies. “This is about getting performance into the system. We know what our bare silicon carbide dies are capable of, but when you connect [these] into the system, you can be introducing parasitics that then degrade that performance,” says Fairchild. “But with this architecture, we can get more performance out of the die we already have.”

Given onsemi’s work with vertical GaN, minimising parasitic inductance and improving device control will be key to performance at higher switching frequencies. “We can now use these devices much more effectively,” she adds.

Silicon architecture
Embedded in a silicon-based package, onsemi’s power platform can use existing fab infrastructure as well as mature validation, simulation and digital twin tools, to provide a faster time to market. Onsemi reckons the platform can accelerate development cycles to as little as four months and help designers to identify design trade-offs earlier, reducing costly late-stage changes.

The silicon architecture promises to deliver low-resistance thermal conduction, rather than having portions of the package occupied by poorly conducting mould compounds and other materials. It also integrates high-voltage isolation into the package, potentially reducing dependence on insulating thermal interface materials (TIMs) and conventional direct bonded copper (DBC) arrangements.

“We’re able to extract heat to drive better performance of the die within the package,” says Fairchild. “We can use high-quality fab processes to get high-voltage isolation embedded directly into this package, enabling a more thermally efficient package and highly integrated power architectures within the package itself.”

Looking ahead, the EPP could also integrate devices built on onsemi’s Treo analog and mixed-signal platform alongside its power technologies. “We have the power, we have the intelligence, and now we have the integration,” says Fairchild, pointing to increasingly integrated power, control and supporting functions in future designs.

“In AI data centres we can draw more power out of the die and better extract the heat and in automotive, we’re getting more efficiency and more range,” she adds.

Indeed, onsemi has just joined forces with Subaru – together the partners will evaluate how the EPP can support electric vehicle traction inverter architectures. According to Fairchild, the Japanese car manufacturer will be using onsemi’s simulation models and engineering samples to understand how the platform can drive power system design, improve efficiency and support future architectures in hybrid and electric vehicles. “Subaru is the first partnership we have announced here,” she says. “Advancing the embedded power platform into the customer evaluation phase and having this interaction is very exciting.”

Onsemi’s Embedded Power Platform uses the silicon wafer as the package, and can integrate Si, SiC and GaN dies as well as drivers, controllers and other supporting power devices. [onsemi]

Hassane El-Khoury, President and CEO onsemi