Accelerating the next era of custom AI silicon

Mohit Gupta, Co-Founder and CEO and Sunil Bhardwaj, Co-Founder of TYLsemi, explains that TYLsemi is the first chiplet platform company to deliver a full portfolio across IO, power delivery, and memory paired with a chiplet-based custom silicon design, integration and supply-chain ownership.

Artificial intelligence is reshaping the technology landscape at an unprecedented pace. As hyperscalers, cloud providers, sovereign technology initiatives, and AI-native companies race to develop ever more powerful computing infrastructure, the semiconductor industry is facing a fundamental challenge: traditional approaches to chip design are struggling to keep pace with the scale, complexity, and economics of modern AI workloads.

Into this environment steps TYLsemi, a company that has emerged from stealth with significant funding and an ambitious mission. Founded by semiconductor industry veterans, TYLsemi is positioning itself as the industry’s first full-stack chiplet platform company, providing customers with a standards-based portfolio encompassing connectivity, power delivery, memory, custom silicon integration, and supply-chain ownership.

According to Founder and CEO Mohit Gupta, the company’s goal is simple but transformative: enable organisations to build custom AI silicon faster, cheaper, and with significantly less risk.

The growing demand for custom AI chips
The rise of AI has created a dramatic shift in the semiconductor landscape. Not long ago, only a handful of companies possessed the resources and expertise necessary to develop custom silicon. Today, that picture looks very different.

“Every hyperscaler, every AI company, and even sovereign initiatives are designing their own custom chips,” Gupta explains.

The drivers are varied. Some organisations seek performance advantages by tailoring silicon to specific workloads. Others want greater control over their technology stacks or independence from external suppliers. Whatever the motivation, the trend is clear: custom silicon has become a strategic asset.

Yet building advanced AI processors has become extraordinarily difficult. Development costs continue to climb as process technologies move toward 2nm and beyond. Engineering teams face immense challenges related to performance, power consumption, memory bandwidth, connectivity, manufacturing yield, packaging complexity, and time-to-market pressures.

TYLsemi’s founding thesis is that companies do not need to reinvent every component of an AI accelerator from scratch.

Instead, they can focus on what differentiates them while leveraging reusable chiplet building blocks for common functions such as connectivity, memory, and power delivery.

That belief formed the basis for the company’s creation.

“We identified a gap in the market,” Gupta says. “Customers repeatedly told us there was a need for a company that could provide those foundational components while helping them integrate everything into custom silicon.”

Why chiplets have become the new standard
Although chiplets have been discussed for many years, Gupta believes the industry has now reached a critical inflection point.

Chiplets, essentially modular blocks of silicon that can be combined into a larger processor package, offer an alternative to traditional monolithic chip designs. Rather than placing every function on a single, massive die, designers can create specialised chiplets optimised for different tasks and manufacturing processes.

Several powerful forces have accelerated this transition.

The first is physics.

For decades, Moore’s Law enabled predictable increases in transistor density and performance. While advances continue, those gains are becoming increasingly difficult and expensive to achieve. At the same time, AI workloads have generated unprecedented demands for compute, memory bandwidth, and connectivity.

“The pain of staying monolithic now exceeds the pain of switching to a chiplet-based design,” Gupta argues.

Economics reinforce the trend.

As process technologies move to 3nm, 2nm, and eventually angstrom-scale nodes, non-recurring engineering (NRE) costs have soared. Large monolithic chips are more expensive to design, manufacture, and validate. Yield challenges become increasingly severe as die sizes increase, making defects more costly.

Chiplet architecture offers a way around those limitations.

By breaking designs into smaller functional blocks, companies can improve yields, optimise process node selection, and reuse proven silicon across multiple products.

At the same time, important industry enablers have emerged.

Advanced packaging technologies such as 2.5D and 3D integration have matured significantly and are now deployed in production at leading foundries and OSATs. Just as importantly, the industry has begun converging around open standards.

The critical role of UCIe
One of the most significant developments for the chiplet ecosystem has been the emergence of the Universal Chiplet Interconnect Express (UCIe) standard.

In the early days of chiplets, fragmentation threatened widespread adoption. Major semiconductor companies developed proprietary die-to-die communication methods, creating interoperability challenges and limiting ecosystem growth.

UCIe is changing that dynamic.

“The industry needed something equivalent to what PCI Express and Ethernet achieved for board-level communication,” Gupta says.

As chiplets became more common, a standard mechanism for die-to-die connectivity became essential. UCIe provides that common language.

The significance extends beyond technical interoperability. Open standards reduce vendor lock-in, encourage ecosystem growth, and allow customers to adopt multi-source procurement strategies. This capability is particularly valuable in the AI era, where supply-chain resilience has become a major strategic concern.

Gupta sees widespread support from hyperscalers as a powerful validation of the standard’s future.

“If organisations with effectively unlimited resources choose to adopt open standards, that tells you something important.”

Looking ahead, he believes chiplet ecosystems could eventually resemble the modular flexibility that engineers once enjoyed with traditional PCB-based component design.

The industry is not yet at that point, but the direction is becoming increasingly clear.

Beyond chiplets: the full-stack platform approach
Many companies in the semiconductor ecosystem provide individual IP blocks or specific chiplet technologies.

TYLsemi believes that approach is insufficient.

The company’s strategy centres on providing an integrated platform spanning three critical dimensions:

• Connectivity
• Power delivery
• Memory

These elements are combined with custom compute integration to create complete silicon solutions.

“When you build silicon, you need to take a system-level view,” Gupta explains.

The challenge is that all three technology vectors are deeply interconnected. Decisions surrounding memory architecture influence power characteristics. Connectivity choices impact performance and efficiency. Power delivery affects both thermal management and compute density.

Optimising one element in isolation often creates constraints elsewhere.

By addressing all three simultaneously, TYLsemi believes it can unlock efficiencies that would otherwise remain inaccessible.

The company’s platform model also supports manufacturing flexibility.

Customers increasingly want the ability to work with multiple foundries, packaging partners, and supply-chain providers. By supporting a multi-source approach, TYLsemi aims to reduce dependency on any single manufacturing pathway.

For Gupta, simply offering one category of chiplet would represent only part of the solution.

“A complete platform provides significantly more value than a standalone component.”

Reducing development time and cost
Among TYLsemi’s most eye-catching claims is the ability to reduce custom AI silicon development costs and timelines by as much as 50%.

Gupta argues that these savings emerge from several sources.

Consider a modern AI inference accelerator.

The compute engine may be manufactured on a cutting-edge 2nm process node, while 3nm is close to leading edge. IO chiplets typically sit on 5/6/7nm or older. Power delivery components may utilise 12nm, 16nm, or even older manufacturing processes.

Traditionally, each of these blocks would require separate development programmes, verification efforts, mask sets, engineering teams, and extensive qualification work.

Reusable chiplets remove much of that burden.

The benefits go far beyond the cost of mask sets alone.

Engineering resources can be redirected toward differentiated compute architectures rather than foundational infrastructure components.

Verification cycles are reduced because existing silicon has already been validated. Packaging strategies can be reused. Development risk is lowered.

The cumulative impact can be substantial.

Gupta points to recent examples, such as OpenAI’s collaboration with Broadcom, where silicon development timelines were dramatically compressed.

“The industry has gone from accepting two-to-three-year chip development cycles to trying to deliver major products annually,” he notes.

Under those conditions, reuse becomes a strategic necessity rather than a convenience. The result is a shift from massive engineering programmes involving hundreds of specialists toward smaller teams delivering products in significantly shorter timeframes.

Sunil Bhardwaj (left) and Mohit Gupta (right)

Solving AI’s power problem
While AI discussions typically focus on compute performance, Gupta argues that power has become one of the industry’s defining challenges.

In many cases, data centre expansion is no longer constrained by chip availability.

Instead, the limiting factor is energy.

Power consumption figures for next-generation AI accelerators continue to rise sharply. Whereas high-performance CPUs and networking equipment once consumed several hundred watts, future AI processors are expected to approach or exceed multiple kilowatts per device.

This trend creates challenges throughout the infrastructure stack, from grid connectivity and facility design through to board-level and package-level power delivery.

TYLsemi’s TYL.Power technology focuses specifically on what Gupta calls the “last mile” of power delivery.

Rather than concentrating solely on bringing power to the package, the company’s objective is to optimise how energy reaches the transistor level inside the device itself.

This requires greater intelligence and control.

TYLsemi aims to provide granular power management capabilities that allow operators and system designers to optimise energy consumption according to workload requirements.

The potential savings are significant.

Gupta estimates that reducing consumption by approximately
300 watts on a 1.5kW accelerator could collectively save ~$10B of dollars across the AI infrastructure ecosystem by the end of the decade. While exact figures will ultimately depend on deployment volumes and energy pricing, the underlying argument is compelling: even small efficiency gains become enormously valuable when multiplied across millions of AI accelerators.

Addressing the connectivity bottleneck
If power is one side of the equation, connectivity is the other.

A growing challenge for semiconductor designers is the widening gap between advances in compute performance and improvements in I/O technology.

Processors are becoming increasingly capable of handling massive volumes of computation, but moving data in
and out of those devices remains difficult.

For AI systems, this creates a significant bottleneck. Raw compute capability provides limited value if data cannot reach the processor quickly enough.

One challenge is that advanced I/O technologies often lag behind the latest logic processes. As organisations adopt cutting-edge nodes for AI compute engines, corresponding SerDes and connectivity technologies may not yet be available or fully optimised.

This is where TYLsemi’s TYL.IO. family enters the picture.

Designed to support PCIe, Ethernet, and emerging connectivity technologies, the platform is intended to give customers access to high-performance interfaces without requiring them to develop those capabilities independently.

The objective is straightforward: allow customers to focus on their AI differentiation while ensuring that connectivity infrastructure keeps pace with increasingly powerful processing engines.

As AI clusters continue expanding and architectures become more distributed, that capability will play an increasingly important role.

Early traction and industry validation
Although TYLsemi remains a young company, it has already secured engagements with tier-one customers and is working alongside TSMC on production samples. According to Gupta, customer response has been overwhelmingly positive.

In some cases, prospective customers have expressed a desire to begin integrating TYLsemi’s solutions immediately.

Of course, semiconductor development timelines remain measured in years rather than months.

The company’s first chiplet samples are expected during the second half of next year, while larger customer programmes incorporating those chiplets are targeting deployments around 2028.

Nevertheless, customer engagement extends far beyond product demonstrations.

TYLsemi actively works with customer architects to gather feedback and ensure future products align with long-term roadmaps.

This collaborative development model is particularly important in a market where semiconductor projects often begin several years before final deployment.

The company’s leadership team also brings considerable industry experience.

Although TYLsemi itself is still in its infancy, Gupta emphasises that the organisation has been built by engineers who have previously delivered high-volume, complex
silicon products. That experience provides credibility with customers evaluating long-term strategic partnerships.

Building on a strong ecosystem
A key pillar of TYLsemi’s strategy is its close relationship with ecosystem partners.

At the centre of that ecosystem sits TSMC, currently serving as the company’s foundry partner.

Gupta describes the collaboration as particularly valuable given TSMC’s track record of enabling advanced semiconductor innovation while maintaining an open foundry model.

Beyond manufacturing, the company relies on cooperation across the broader semiconductor value chain, including packaging providers, OSAT partners, EDA vendors, and system integrators.

The success of chiplet-based design ultimately depends on ecosystem participation.

No single company can solve all the challenges associated with advanced AI infrastructure.

Instead, progress relies on standards, interoperability, and collaboration across multiple technology domains.

A future built on heterogeneous silicon
Looking ahead, Gupta envisions a future where building custom silicon becomes dramatically more accessible.

His goal is not to help customers establish internal semiconductor companies. Rather, it is to eliminate the need for them to do so.

In that future, organisations focus on the elements that make them unique, whether that is compute architecture, software frameworks, compilers, or AI models. Specialist partners such as TYLsemi would handle the complexities of transforming those ideas into physical silicon. Ultimately, Gupta sees chiplets enabling a truly heterogeneous semiconductor ecosystem.

In this model, individual dies could be sourced from multiple regions, built on different process technologies, and integrated into unified products through advanced packaging techniques.

While significant challenges remain, the industry has already demonstrated an ability to overcome obstacles that once seemed insurmountable.

Technologies such as 3D packaging and advanced die stacking have moved from conceptual research to commercial reality in just a few years.

For Gupta, this progress suggests that even more ambitious visions may be achievable.

Conclusion
The semiconductor industry is entering a period of profound transformation. AI is driving unprecedented demand for custom silicon, while simultaneously exposing the limitations of traditional monolithic design methodologies.

TYLsemi believes the answer lies in a modular, standards-based future built around chiplets.

By combining connectivity, power delivery, memory, custom integration capabilities, and ecosystem partnerships into a single platform, the company is seeking to simplify one of the most complex engineering challenges in modern technology.

Whether that vision ultimately reshapes the industry remains to be seen. However, the forces driving chiplet adoption appear increasingly powerful: rising costs, growing design complexity, mounting power constraints, and relentless pressure to accelerate innovation.

As AI infrastructure continues to scale, the ability to build faster, more efficient, and more flexible silicon could become one of the defining competitive advantages of the next decade.

And if Gupta’s vision proves correct, future companies looking to build AI chips may spend far less time worrying about semiconductor development itself and far more time focusing on the workloads that make their solutions unique.