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High Productivity DRIE For Volume 3D-SIP And MEMS

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The future of DRIE technology is now widening thanks to its recognition as an enabling technology. Manufacturers are looking to increase capacity by improving throughputs and controlling costs. Alcatel describes its productivity enhancements.

 
The latest developments in MEMS, wafer level packaging [1] and active and passive electronic devices using deep reactive ion etch (DRIE) have recently allowed the introduction of superior product performances. The future of DRIE technology is now widening thanks to its ever-increasing recognition as an enabling technology. The use of DRIE in high volume applications like mobile phones or automotive sensors is now a reality and manufacturers are always looking for ways to increase capacity by improving throughputs and controlling costs.

Unlike CMOS applications, etching high aspect ratio structures of up to 100:1 [2] with DRIE, suffers from long process times that result in throughputs of only few wafers per hour. The first way to improve throughput is to increase the etching rate of the Bosch process [3]. It is obvious that even the latest announced etching rates are not sufficient; in this paper, experimental work will be presented to show that etch rates in the range 30-35µm/mn are achievable. Another way to improve the overall productivity of the DRIE step is to optimise production parameters such as process uniformity, process stability, process yield, system production time, reduction of consumable use and scheduled maintenance. Solutions that result in dramatically increasing the wafer throughput and significantly reducing the cost of ownership (CoO) will be presented.

Experimental set up
The experiments in this study have been carried out on an Alcatel AMS 200 "I-Productivity" DRIE etching tool, optimised for high volume manufacturing (Figure 1).


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"I-Productivity" is a new generation after Alcatel's "I-Speeder" series and is fitted with a patented high-density ICP type plasma source. The source is fixed on top of a diffusion chamber surrounded by a number of permanent magnets. This arrangement allows an optimised process gas delivery as well as high ion density uniformity. The "I-Productivity" system can be equipped with mechanical or electrostatic wafer clamping solutions. All of the experiments have been performed with patterned 150mm diameter silicon wafers.The Alcatel DRIE tools are offered with several types of process. The most popular one is the well-known Bosch process based on the use of alternate steps of SF6 and C4F8. The SF6 is used to etch the Si, and the C4F8 to passivate the surfaces and to achieve anisotropic silicon etch. This alternation of etching and passivation steps results in a waving side wall profile, also commonly called scalloping. With the control of the gas flows and pressures, this scalloping can be significantly reduced, to as low as 14nm.

Higher productivity solutions
In 2002, the "I-Speeder" project [4], developed with Bosch and PerkinElmer, resulted in tools that had the fastest etch rate for silicon etching in the market. The latest "I-Productivity" project has resulted in further etch rate improvement and is now exceeding 30µm/mn with an excellent etch depth uniformity.


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To achieve a high process yield requires a good depth uniformity as well as good profile uniformity. Such performances can only be obtained with a well-designed process chamber, which leads to an uniform gas phase, uniform plasma, and uniform temperature range across the wafer.

Part of Alcatel's success is due to its extensive R&D division, and the use of simulation software to achieve the best pump performance possible. One of these 2D software programs [5] has been used to study the neutral flows at the wafer level for different process regimes on the AMS 200 "IProductivity" tool. It has also allowed us to optimise the Bosch process in order to achieve the best etch rate and with high etch depth uniformity. Optimised simulation now shows excellent gas velocity uniformity above the wafer surface. The inherent non uniformity of ICP plasmas has been dramatically reduced in the "I-Productivity" system through both chamber dimensioning and magnetic multipolar confinement. Magnet strength and spacing together with inner chamber diameter have been optimised regarding ion uniformity while providing the maximum pumping speed for processing 200mm wafers. With such 200mm wafers, the potential plasma uniformity is better than 5%, which also leads to a comparable etch depth uniformity.

The surface temperature at the wafer level is a key parameter to achieve good depth and profile uniformity. Furthermore, many three-dimensional systems in package (3D-SiP) applications have strict thermal budgets in terms of the maximum process temperature allowed, due to the delicate devices and components on the wafer. After the Bosch process etch step, which is not temperature sensitive, the passivation step shows a linear decrease of deposition rate proportional to the temperature.


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If the edge of the wafer is cooler than the centre, then the quantity of polymer deposited at the edge during the C4F8 step will be higher. Since the SF6 step will remove the same quantity of polymer all over the wafer, more polymer will therefore remain at the edge. The consequence of this phenomenon is "micromasking", leading to a non uniform etch depth and profile across the wafer.

During the ICP DRIE of silicon in fluorine chemistry, a Si wafer receives energy on its top side and this energy will heat up this surface. On the back side, however, the wafer is cooled by the chuck through the He backside gas pressure. The final surface temperature depends of the ratio deposited on the surface and the amount of energy evacuated by the chuck. The energy arriving at the wafer surface is the sum of the energies coming from the ion bombardment, the etching chemical reaction and the radiation of the plasma and hot surfaces.

From all the energies arriving at the wafer surface, the most important one is the energy coming from the chemical reaction of the silicon with the fluorine gas:


Si (s) + 4_F (g) ( SiF4 (g) + (G0=435 Kcal/mol


This energy (PE) is proportional to the amount of Si removed per unit time and surface area:


PE = [Si mol/ (T _ Mmol)] _ (G0 with Mmol being the molar mass (28g/mol); Si mol, the quantity of removed Si; T, the time; and, (G0, the chemical reaction energy.


Therefore, PE is directly proportional to the etch rate and the exposed area.


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That means that a significant increase of the etch rate requires an efficient chuck design to evacuate all the heat generated at the wafer level. In order to evacuate all this heat and achieve the best temperature uniformity, Alcatel has designed a "P" type electrostatic chuck (ESC) with an innovative design, which allows the temperature to be adjusted with regard to the wafer patterns.

For a given process, the "P" type ESC, gives a uniform temperature of (0.15°C across the wafer, with an excellent thermal conductivity. The improved cooling capability of the ESC "P" allows for the development of some new processes that lead to higher etch rates.

Another way to increase the process yield is to reduce the edge exclusion, in order to increase the number of properly etched features. The new ESC "P" has been specially designed to avoid any distortion of the plasma sheath at the wafer edge, and therefore has an edge exclusion not exceeding 3mm.


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Solutions for increased uptime
The C4F8 used for the passivation during the Bosch process creates a polymer that is deposited on all the cold surfaces in the process chamber. The accumulation of this polymer on the chamber wall creates the need for frequent mechanical cleanings and conditioning procedures, leading to extended downtime. To avoid the need for wet cleaning to remove these polymers from the process chamber wall, Alcatel developed a unique patented heated liner [6]. The liner controls the temperature to avoid polymer deposition. The design avoids excessive heating of the outside of the process chamber and minimises electrical consumption. Furthermore, the heated liner maintains a constant plasma condition of the chamber wall, resulting in a silicon etch rate that is very stable even after multiple plasma hours.


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For high volume production, the CoO is an important parameter to take into account. DRIE ICP is often used to etch micron or sub-micron features to an etch depth from a few up to hundreds of microns. Compared to typical Microelectronic processes, the etch duration is usually longer even with the typical ten to hundred times faster etch rates. The most efficient way to reduce the CoO is to lower the running costs of the tool. There are several ways to do this. One way is to increase the etch rate, another is to reduce the C4F8 consumption, a quite expensive gas. As the C4F8 step is more efficient at high pressure, the hardware was modified to allow different pressures for the SF6 and C4F8 steps. The C4F8, therefore, can be set up at high pressure whatever the value of SF6 pressure. Another way to improve the CoO is to increase the availability of the chamber for processing by using the heated liner, to reduce cleaning frequency and duration. The low electrical consumption of the heated liner further adds to the low CoO. In addition to the above hardware improvements, the tool design was also significantly modified to reduce the cost and number of spare parts.


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Benefits for high volume
One notable application using all the benefits of the "I-Productivity" DRIE etcher was a high volume process for integration of passive components. Compared to the previous "ISpeeder" performance, "I-Productivity" improved the etch rate by 43%, and, thanks to the reduced cleaning frequency, throughput was increased 83%. The higher process range allowed for a decrease of 42% in the consumption of the expensive C4F8 gas (Figure 9). "I-Productivity" benefits can also be applied to the high volume MEMS market, such as silicon microphone or inkjet head applications, along with power devices, passive components, and the emerging 3D applications (interconnection, CMOS imagers...).


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Conclusion
The latest developments and improvements, as applied to the Alcatel AMS 200 "I-Productivity" tool, result in much higher production performance, thanks to lower etch drift, extended cleaning frequency, limited edge exclusion, higher etch rate, better process stability and higher etch uniformity. It is now possible to offer an unrivalled set of hardware and process solutions, using the "IProductivity" DRIE tools for high volume manufacturing, as applied to 3D-SiP and MEMS.


REFERENCES
[1] M. Puech et al. 8th SEMI Microsystem/MEMS Seminar, Dec. 2nd, 2004, pp 143-152.
[2] F. Marty et al. "Advanced Silicon Etching Techniques Based on Deep Reactive Ion Etching for Silicon HARMS and 3D Micro and Nano Structures", ASME European Micro and Nanosystem Conference EMN'04, Oct. 20-21, pp. 25-28.
[3] F. Laermer., A. Schilp, "Method of Anisotropically Etching Si", US patent 5,501,893.
[4] European Commission Framework V, IST-1999-11261, Semiconductor Equipment Assessement (SEA): "I-SPEEDER".
[5] FLUENT(r) flow modelling software.
[6] M. Puech, PCT Patent: WO 2004008477.



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