Memory In Bed With SOI
Toshiba succeeded in forming embedded DRAM system LSI on an SOI wafer by developing a new DRAM memory cell technology that makes use of the characteristics of SOI wafer itself, eliminating the necessity of capacitors where current DRAM cells store data. The new memory cell technology, dubbed floating body cell (FBC), will be used for embedded DRAM system LSI for the 45nm generation on at Toshiba.
A conventional DRAM cell consists of a capacitor, where electric charge is stored, and a transistor that functions as a switch. The newly developed FBC does not have a capacitor and memorises data by storing the electric charge in the transistor. Since the transistor works as both capacitor and electric switch, the cell area is half that of a conventional DRAM cell.
Compatibility between the manufacturing processes of DRAM cells and logic ICs is a crucial issue for the development of embedded DRAM cell technology for SOI-based system LSIs. For full compatibility without any degradation in performance, a poly-Si plug - a buffer layer of poly-silicon - is formed in the contact area of the memory cell.
Toshibas experimental 96kbit cell array achieved successful operation in all bits, a 36nsec access time, a 30nsec data switching time, and a 500msec data retention time (at 85C). These results demonstrated to Toshiba that the new FBC technology could be applied to system LSIs integrating DRAM cells with Mbit or greater memory capacity.
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Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.
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