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Imec pushes the limits of EUV lithography single exposure for future logic and memory

Imec has made considerable progress towards enabling extreme ultraviolet (EUV) lithography single exposure of N5 32 nm pitch metal-2 layers and of 36 nm pitch contact holes. Greg McIntyre, Peter De Bisschop, Danilo De Simone, Frederic Lazzarino and Victor Blanco from the imec patterning team explain some of the key steps and highlight the impact on the semiconductor industry.

With Pioneer Works starting in the late 1980’s, the road towards EUV infrastructure development and readiness has been a challenging one. Although EUV lithography has a number of similarities to, e.g., 193 nm optical lithography, it presents unique characteristics. For example, with a short imaging wavelength of 13.5nm, EUV radiation is not transmitted through ambient air and is strongly absorbed by all solid materials. Challenges to EUV development included for example the light source (with sufficient power to enable cost-effective production), mask inspection and defectivity, and photoresist issues.

The successful integration of EUV lithography into semiconductor manufacturing would however bring many benefits. For example, the ability to print features with single exposure EUV lithography instead of with multi-patterning 193nm lithography leads to enhanced process simplification and reduced cost per wafer. This has driven the semiconductor industry to continue improving on the scanner, source and mask infrastructure.

In recent years, significant progress has been made for all critical issues. For example, with a recent power demonstration of 250 W, the light source now has shown capability to meet the roadmap target and ensure sufficient throughput in terms of wafers per hour. First insertion of EUV lithography in high-volume manufacturing is expected in the critical back-end-of-line (BEOL) metal and via layers of the foundry N7 logic technology node (with metal pitches in the range of 36-40 nm), in the 2018-2019 time frame.

Fig 1: Benefits of using EUV lithography single exposure in terms of wafer cost and (right) process simplicity

Exploring the options for N5 and beyond

In the meantime, imec and its partners are weighing the options for the following node (32nm pitch and below). At these dense pitches, various patterning approaches are being considered that differ in terms of complexity, wafer cost, and time to yield. These approaches include variations of EUV multi-patterning, hybrid EUV and immersion multi-patterning, and EUV single exposure. Last year, at the 2017 SPIE Advanced Lithography Conference, imec presented many advances in hybrid multi-patterning (hybrid 193i-EUV) by combining, e.g., 193 nm immersion-based self aligned quadrupole patterning (SAQP) of 32 nm pitch metal lines with a direct EUV print of the block layers.

At the same time, imec has been pushing the limits of EUV single exposure for logic and memory technology nodes, as further benefits can be expected from a single exposure step in terms of process simplicity, wafer cost and time to yield. For example, imec calculated a 20% reduction in wafer cost when transitioning from an all 193 nm immersion-based solution to a solution where blocks and vias are patterned with EUV single exposure. A further 3.2% reduction is expected for EUV single patterning of the critical metal lines and vias. Equally important is time-to-yield, which heavily depends on process complexity. The example of the figure below shows a reduction in roughly 60% required process steps for the hybrid 193i-EUV technique when compared to the all immersion-based solution, and roughly 80% with EUV single exposure. This can translate to days or weeks reduction in the turn-around time for a single wafer lot. Considering a very large number of lots are required to develop a technology, this can result in a significant advantage.

Yet, several challenges still need to be tackled before these small and dense features can be patterned with EUV single exposure. Despite tremendous progress, critical issues remain with respect to e.g. the resist performance, stochastic failures, photomask, metrology and inspections and pattern transfer. In addition, a more fundamental understanding of the critical EUV processes, such as the resist reaction mechanisms, is still lacking. At the 2018 SPIE Advanced Lithography Conference, imec has demonstrated promising advances in all these areas, focusing on two primary use cases: the logic N5 32 nm pitch metal-2 layer, and 36 nm pitch contact holes for dense DRAM applications.

Fig 2: Stochastic printing failures observed after printing (top) lines/spaces, and (bottom) contact holes.

EUV stochastic printing failures: limiting the applicability of EUV lithography

The term ‘stochastic effects’ refers to random, local variability that occurs between structures that should in principle print identically. These effects have always been part of lithography. Best known is critical dimension (CD) variability, which is quantified through metrics such as line-width roughness, line-edge roughness or local CD uniformity. Over the years, these metrics have been intensively studied. However, next to CD variability, stochastic effects can give rise to local, random failures such as micro-bridges and broken lines (when printing lines/spaces), or bridging contacts and missing contacts (when printing contact arrays). These failures are less understood. They are typically generated throughout the complex resist pattern-formation process itself. Now that dimensions are shrinking and less photons are available during EUV exposure compared with traditional 193nm (immersion) lithography, these failures are expected to increasingly impact the yield of future devices.

Fig 3: Example of the impact of failure mechanisms on the available target CDrange for dense lines/spaces (36nm pitch). Exposure dose was at ~32mJ/cm2.

To gain more fundamental insights, imec has continued its systematic study of stochastic failures, for both lines/spaces and contact arrays. The team focused on the quantification of the stochastic failures and investigated their dependency on experimental parameters (such as dose, resist, CD). The final goal was to understand how these stochastic effects limit the applicability of EUV lithography, and to identify the knobs that allow minimizing the number of failures. The new method for quantifying the stochastic printing failures consists in automatically counting the relative number of failures (i.e., the missing and bridging contacts, and the line breaking and micro-bridges) that are visible in a series of SEM images. Although this SEM-based technique can only be applied to a limited inspection area, the method is ideally suited for determining the process parameters affecting the number of stochastic failures.

The number of stochastic failures is found to depend on many experimental parameters, providing several knobs for optimization. For example, it largely depends on target CD (line or space), or on the target diameter of the contact hole. E.g., micro-bridges and missing contacts are more abundant as the width of the space or the size of the contact is smaller. This behavior also varies with pitch: for dense pitches, the number of missing (and bridging) contacts increases rapidly as the size of the contacts becomes smaller (or larger). These stochastic failures limit the available CD-window – the CD-range for which neither type of printing failure is observed – and hence the applicability of EUV lithography.