Process Development
During the
life cycle of a car, several of the original integrated circuits (IC) that
are designed in when the car is launched become obsolete - forcing car
manufacturers to carry out expensive redesigns. By physically separating the
digital logic element of a chip from the I/O and creating two chips within
one package, the new ActivePackage concept solves this problem, claims
Micronas, along with several other difficulties caused through short IC life
cycles. Up to now, it has been impossible to connect the latest controllers
directly to the electrical system in the car because they could not operate
with such high voltages.
With the ActivePackage approach, there will be two chips per IC package -
the logic chip and the peripheral chip. This decoupling allows the core
logic to be manufactured in the latest process technology. The programmable
peripheral chip converts the core logic's electrical parameters for external
communication. This enables car manufacturers to design ICs into their cars
with "frozen" electrical and mechanical parameters, saving time and money in
the future.
The ActivePackage approach guarantees not only that the electrical
parameters remain constant over many generations, but also the pin-out and
the mechanical characteristics of the package. The programmable peripheral
chip acts as part of the IC package and provides it with a whole new quality
- hence the ActivePackage name.
"Up until now, car manufacturers have been forced to redesign a car's
electronic control unit as soon as the IC manufacturer made a product group
obsolete," said Klaus Heberle, vice president for automotive products at
Micronas. "Besides being expensive, the car manufacturer has to go through a
learning curve to maximise IC performance. This has proven to be a very
serious problem for the adoption of electronics in cars. With ActivePackage,
car manufacturers benefit from the progresses in process technology and can
integrate chips with a greater level of performance while eliminating the
need for redesign."
Micronas believes that chip manufacturers will also benefit as they will not
need special roadmaps for their automotive clients. The functional block can
always be manufactured in the latest technology and integrated into the
ActivePackage, while other characteristics remain unchanged - effectively
solving the lifetime supply problem through adopting a platform approach.
The ActivePackage concept requires multi-chip-packages, which can today be
manufactured cost-effectively with high yields. The ICs are bonded on the
lead frame and electrically connected with each other. Both steps are part
of the assembly and bonding process with no other process steps required.
Micronas expects that the demand for such chips will be such that the
required raw materials and production lines will be available on a long-term
basis.
ST Assembly Test Services (STATS) has qualified a "total" system-in-package
(SiP) solution for PBGA, stPBGA and LGA packages along with surface mount
manufacturing capabilities. SiP integrates one or more ICs, passives, RF and
other components in a package. STATS makes early engagements with customers
at the system architecture and partitioning stage to provide thermal,
electrical, and mechanical characterisation concurrently with test planning
as part of the overall design and layout process.
Dr Han Byung Joon, STATS chief technology officer, comments: "SiP has become
increasingly popular as it allows separately optimised technologies such as
GaAs, SiGe and silicon to be integrated on a single platform."
SiP is currently used to integrate baseband and RF devices for cellular, GPS
and Bluetooth products.
IBM and ILS Technology claimed installation of the world's first
e-diagnostics solution designed to enable remote tool monitoring,
tool-take-over and engineering collaboration under a single full-fab
governance model. The solution has been under test at IBM's 300mm wafer fab
in Fishkill, New York state, as result of a partnership announced by the two
companies last year.
The solution has three key elements. First, ILS Technology's e-Centre
addresses access, security and safety issues with a fab-wide governance
model that provides a secure, scaleable platform for e-diagnostics
processes. Second, IBM's Isolation Network, designed, built and supported by
IBM Global Services, prevents unauthorised cross-talk from tool-to-tool by
isolating semiconductor manufacturing equipment from the enterprise and each
other. Third, ILS Technology's ServiceNet, built on IBM technology and
experience, provides a dedicated virtual private network (VPN) that enables
a connect-once, access-all approach to secure VPN connectivity.
Furthermore, remote take-over capability gives experts the ability to fix
tool problems no matter where in the world they sit, without compromising a
fab customers' or an equipment manufacturers' critical data or the safety of
the people involved in the process.
Both e-Centre and ServiceNet are open-architecture (non-proprietary),
commercially available, neutral solutions that are built on International
SEMATECH (ISMT) guidelines.
The installation at East Fishkill started with ion implantation and rapid
thermal processing (RTP) tools manufactured and supported by Axcelis
Technologies. All of these tools are designed with an on-board process
control and diagnostic capability that integrates with the open architecture
provided by e-Centre. IBM's 2003 plan for deployment of the ILS solution
will include all critical processes throughout the fab.
In July 2002, IBM and ILS announced the two companies would jointly market
and sell ILS' e-Centre and ServiceNet solutions. In this non-exclusive
alliance, ILS will lead with IBM's hardware and middleware as platforms of
choice. IBM will lead with ILS as the e-diagnostics solution of choice and
provide global marketing and integration support for joint IBM and ILS
solution deployments.
International SEMATECH's has made its first public release on a new Industry
Economic Model (IEM). It is hoped that a wealth of new perspectives will
help sharpen and proliferate the statistical forecast tool, according to its
main developer.
Denis Fandel, IEM project manager, reports that approximately 50 diverse
managers from semiconductor industry suppliers and manufacturers offered
"very useful feedback" on the assumptions, techniques and algorithms
underlying the IEM during a day-long Global Economic Symposium held May 21,
2003, in Oregon.
The IEM is a software package that can analyse various aspects of
semiconductor economics in terms of capacity, supplier markets, and
productivity as influenced by technology assumptions, product demand trends
and business dynamics.
The IEM is based on simulating industry response from three basic but at
times competing forces: parameters from the International Technology Roadmap
for Semiconductors (ITRS), manufacturing and supplier assumptions from the
ISMT Cost Resource Model (CRM) and a marketing forecast for product demand.
Surveys on the model were distributed during the symposium and the IEM might
be adjusted as a result to make it more relevant and effective to a broader
section of the industry.
"Initially, we want to beta test the model with various types of users, so
that its operating principles become universally accepted," says Fandel. "As
we increase the usage of it, professionals either can start adopting it or
create derivatives of it for their own use. That way, the model could become
the de facto standard for how the industry evaluates itself."
Fandel comments: "The model is sort of like a software version of a
strategic planning department, for companies that can't afford to staff
one."
A recent, half-day mask yield management workshop sponsored by International
SEMATECH (ISMT) came to the conclusion that commercially available software
to snare mask defects early in the production cycle seems an idea whose time
has come. With the cost of advanced semiconductor photomask sets approaching
$1mn apiece, the need for sophisticated, standardised, commercially
available software is vital.
"Mask yield is the overwhelming driver for mask costs and delivery times,"
said Kurt Kimmel, ISMT's outgoing Mask Program manager and workshop chair.
"Within yield, the main drivers are defects and CD [critical dimension]
control."
Kimmel pointed out that automated yield management, long a staple process
for semiconductor manufacturing, has been slow in coming to the photomask
world - mainly because masks have been heterogeneous products not produced
in quantities large enough to justify the cost of automated defect
detection. But as the complexity and cost of mask sets has soared, it has
become vital to catch defects as early as possible, he said.
"Unlike the wafer world, mask yield is unique, because the lot size is one,"
Kimmel said. "If you're not at 100%, your next best yield is 50% - and that
kind of loss rate is difficult to recover from."
Applied Materials has introduced a new 300mm electrochemical plating (ECP)
system that the company claims overcomes the limitations of existing plating
technology for current generation manufacturing and groundbreaking
capability for 65nm and beyond copper chip development.
Key to the new SlimCell system is an individual-cell chemistry that enables
multi-step ECP processing.
"Much like the 1980s revolutionary shift from batch to single-wafer
processing, the SlimCell system breaks away from the limitations of the
batch chemistry approach to electroplating to set new standards in
performance and tool extendibility," said Russell Ellwanger, vice president
and general manager of Applied Materials' PPC product group.
SUSS MicroTec announced new capabilities for cost-effective 1X full-field
lithography (1XFFL) with a package of four new technologies. Known
collectively as SupraYield, the enhancements provide a high-performance
1XFFL solution for advanced thick-resist applications, such as wafer-level
packaging, MEMS and optoelectronics.
SUSS claims that 1XFFL systems enhanced with SupraYield Technology can
double throughput, achieve 1micron resolution and submicron overlay and
reduce lithography costs by up to 66% compared with steppers.
"SUSS 1XFFL systems efficiently expose the entire wafer, up to 300mm, in one
step, allowing twice the throughput at about half of the purchase price of
comparable 1X stepper technology," said Dr Franz Richter, president and CEO
of SUSS MicroTec.
SupraYield is a package of four technologies: Mask Pellicle Technology
(MPT), ThermAlign Chuck, advanced photoresists and Large Clearfield Mask
Movement.
AngelTech Live III: Join us on 12 April 2021!
AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!
Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.
2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.
We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.
We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.
Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.
Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.
So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.
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