IMEC has launched two industrial affiliation programmes (IIAPs) targeting sub-45nm processes. The first programme aims at improving device performance by implementing strained silicon (Si) in the transistor channel for scaled planar MOS devices. The second will exploit the high-mobility features of germanium (Ge) to fabricate high-performance CMOS transistors. The programmes are inter-linked with IMEC's present advanced CMOS research programmes.

IMEC has launched two industrial affiliation programmes (IIAPs) targeting sub-45nm processes. The first programme aims at improving device performance by implementing strained silicon (Si) in the transistor channel for scaled planar MOS devices. The second will exploit the high-mobility features of germanium (Ge) to fabricate high-performance CMOS transistors. The programmes are inter-linked with IMEC's present advanced CMOS research programmes.

"Implementation of high-mobility layers and advanced source/drain engineering solutions in scaled planar devices" will investigate improved carrier mobility in strained silicon structures. The research covers strained Si formation on top of SRB (strain relaxed buffer) layers, silicide formation, shallow junctions and extensions, compatibility issues, advanced strain characterisation and device demonstration.

IMEC has already researched strained Si on SiGe transistors, ultra-shallow junctions and silicides and has developed an innovative production technique for thin SRBs with a total thickness of less than 200nm. The structure achieved superior properties compared to the industry standard. Moreover, SRB can also be applied in a selective way on pre-formed isolation structures such as STI (shallow-trench isolation). Besides that, IMEC has shown world-record mobility figures for holes in hetero-pMOS with strained SiGe.

The Ge CMOS devices programme targets the feasibility demonstration of fabricating Ge devices compatible with a state-of-the-art Si production line. These Ge devices will include high-k materials and metal gates to obtain aggressively scaled EOT (equivalent oxide thickness) targets.

The programmes will initially use 200mm equipment but will gradually transfer to 300mm equipment in IMEC's new facility now under construction. Potential partners are leading IC and wafer manufacturers.

To support the germanium programme, IMEC, Soitec and Umicore have joined forces to enable fabrication of germanium-on-insulator (GeOI) substrates and development of semiconductor devices on these substrates.

Germanium has some attractive chemical and electrical properties as a potential replacement for planar silicon, which is unlikely to accommodate the rigorous scaling requirements of sub-45nm geometries. The material's carrier mobility is higher than that of silicon for both electrons and holes. Germanium is expected to be compatible with high-k materials used as a gate insulator. Moreover, dopant activation temperatures are much lower than those required by silicon, facilitating the formation of shallow junctions. These features create a need for high-quality Ge-based substrates.

Each participant in this collaborative effort will contribute state-of-the-art technological expertise in its respective field, sharing data and findings throughout the process.

Umicore has a background in the commercialisation and development of germanium substrates and will be responsible for the development and production of 200mm and 300mm crystalline germanium wafers.

Soitec will apply its proprietary Smart Cut process to transfer a germanium layer from these wafers to form a germanium-on-insulator (GeOI) wafer.

IMEC will bring its extensive knowledge of high-k materials, metal gates, device development and characterisation and process integration to develop a high-k layer deposition technique for GeOI substrates, as well as defect inspection techniques for the completed GeOI wafers. IMEC will also fabricate advanced devices to demonstrate the potential of GeOI substrates for the sub-45nm node.

"To solve the channel mobility and gate leakage current problems present in scaled silicon devices, we believe that alternative concepts such as the combination of high-k dielectrics with germanium need to be examined," says Gilbert Declerck, president and CEO of IMEC.

In March this year, Soitec competitor Silicon Genesis detailed its proposals to develop GeOI (Bulletin 476, March 27, 2003).

AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

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