Philips and the European IMEC research centre have completed fabrication of 65nm CMOS devices with good electrical performance as the second milestone within their strategic partnership.

Philips and the European IMEC research centre have completed fabrication of 65nm CMOS devices with good electrical performance as the second milestone within their strategic partnership.

Philips Research and IMEC formed a strategic alliance in 2000 to explore the key processing and integration steps in advanced CMOS. Work on the 65nm CMOS technology node began in early 2002 after a successful first step had been made in the joint exploration of the 90nm technology.

The 65nm technology is based on a scaled version of planar 90nm bulk CMOS. Devices feature 45nm gate length, equivalent oxide thickness of 14Angstrom, 100nm thick polysilicon gates and sub-20nm junction depths.

Gate dielectric recipes were optimised through plasma nitridation of ultra-thin oxides for reduction of gate leakage and suppression of boron penetration. Shallow source/drain engineering was performed using ultra-low energy implantation in combination with germanium pre-amorphisation and fluorine co-implantation (PMOST) and fast ramping high-temperature spike anneals.

Low-temperature deposition techniques were introduced in the back-end for spacer, salicide blocking and PMD (pre-metal dielectric) layers to avoid excessive dopant diffusion and de-activation. Finally an advanced two-step nickel salicidation was successfully integrated leading to improved control of line width effects as well as reduced junction leakage and contact resistance.

Drive currents of 790microA/micron for NMOST and 355microA/micron for PMOST were obtained at Vdd=1V and an off-state current of 100nA/micron. Devices exhibit good short channel effect control.

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