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Intel Strains Ahead With 90nm

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Intel gave details of a strained silicon transistor that is being used in its next-generation 90nm process. The process is to be ramped this year at the company’s 300mm fabs in Hillsboro, Oregon, and Albuquerque, New Mexico. And next year (H1 2004), the process will come to Europe at Intel’s fab in Leixlip, Ireland.
Intel gave details of a strained silicon transistor that is being used in its next-generation 90nm process. The process is to be ramped this year at the company's 300mm fabs in Hillsboro, Oregon, and Albuquerque, New Mexico. And next year (H1 2004), the process will come to Europe at Intel's fab in Leixlip, Ireland.


A fab in Arizona (F22) will be next to adopt the process. The technology is being ramped to volume for producing Pentium and Centrino microprocessors.


The company says that the process has experience rapid yield improvement and that the defect density is now down to the levels needed for high volume manufacturing.
The process strains the PMOS and NMOS transistors in different way. The level of strain is of the order of 1%.


The PMOS transistor has a silicon germanium source/drain structure on which a strained silicon channel is deposited. This improves drive current by 25% compared with non-strained devices.


The NMOS transistor has a normal source/drain. The strain is introduced into the channel through a silicon nitride (Si3N4) cap layer on the transistor. This improves drive current by 10%.


The different approaches have allowed Intel to optimise the different transistor types for an added process cost of only 2%, the company says. Mark Bohr, director of process architecture and integration, says that the process has already been scaled to 65nm and may be useful beyond that.


Other features of the 90nm process are a physical gate oxide thickness of 1.2nm, a nickel silicide replacing cobalt silicide and a carbon doped oxide intermetal dielectric. A 6-transistor static RAM (6-T SRAM) structure built on the process has a cell measuring 1.0micron2.


Intel will be presenting a paper on the transistors at the IEEE International Electron Devices Meeting (iedm) in December.



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