A logical switch to the vertical direction

Surging sales of wearable devices will drive a new era for the IC, with planar FETs replaced with vertical gate-all-around transistors

BY KATSUHIRO TOMIOKA FROM HOKKAIDO UNIVERSITY

WHEN COMMERCIALIZATION of the IC began back in the 1960s microprocessors would feature a dozen or so transistors, each with dimensions of tens of microns. In the intervening years we’ve come an awfully long way. Progressing at rates described by Moore’s Law and Dennard Scaling, we have been on an exponential trajectory. While its not been easy at times, requiring the likes of the introduction of a high-κ gate oxide, metal gates, strained silicon and multi-gate architectures to keep up the pace, continued advances have ensured that the world’s leading fabs are now churning out ICs with 50 billion FETs. The big question is this: given the exceptional miniaturization of the FET, how will researchers extend LSI from now on?

While these researchers ponder this, they must consider how the pandemic has changed the way we use electronic devices, and how electronics are developed. We now live in a world where there are fewer physical spaces and cyber spaces are on the rise. This has meant that working remotely is now the norm in many sectors, and socialising on-line is commonplace. There is also more interest in wearable augmented-reality devices. The likes of smart glasses, earphones, wrist bands and rings, previously thought of as gadgets of the distant future, are now the technologies we want to soon inhabit our world.

Getting there requires addressing concerns over wearable devices. Compared to smartphones and other forms of portable electronics, they have limited functionality. It also challenging to make them small enough, so that they are not cumbersome. Success on both fronts demands a new generation of high-performance LSIs to serve in a post-5G era. Our team at Hokkaido University, Japan, is tackling this challenge by developing a number of promising technologies. We have considered performance per unit volume, finding that when the system performance is represented by memory bytes, this plummets with the miniaturization of the device size (see Table 1). Due to this trend, we are convinced that wearable devices of the post-5G era need to contain a high-performance computing system.

What will the transistor technology look like in such a system? Consequences of miniaturisation indicate that it can’t be based on planar integration, the mainstream architecture since the 1960s. We can also rule out the stacking of LSI chips – the so-called 3D integration or chiplets – due to serious thermal management problems. So a new integration schemes is needed, delivering much denser devices in a smaller footprint than modern LSI. This approach demands alternative switches, used to create small, high-performance architectures with ultra-low thermal dissipation.

Four ways forward
We are investigating four different approaches for producing modern FETs that could fulfil these requirements: an alternative FET structure, different channel materials, a new switching mechanism and a refined integration scheme (all are outlined in Figure 1).

One simple approach to decreasing the FET’s power consumption is to lower its supply voltage. That’s because the active power of an IC is proportional to the square of the supply voltage; and the stand-by power of an IC is proportional to the supply voltage, and the off-state leakage current.

An option for decreasing the off-state leakage current is to shift to a gate-all-around architecture. With this design, the gate metal wraps all around the channel to provide the best electrostatic control of the gate.

When it comes to replacing the channel material, there are several strong candidates for taking the place of silicon. Contenders include III-Vs, germanium, and two-dimensional transition-metal dichalcogenides. All promise to provide a high on-state current under low bias, thanks to their high carrier mobility and low electron/hole effective mass. However, the latter is actually a mixed blessing, as the small effective mass also results in a high tunnelling leakage current. So, when these alternatives to silicon are deployed in a multi-gate architecture, efforts must be directed at driving down the leakage current.

Another issue that can arise when using higher mobility materials is that there is an inherent mobility mismatch between the n- and p-channels – this is a problem in CMOS architectures. It may not seem a big issue, given that designers of LSI can adjust the device area to ensure current matching between n-channel and p-channel FETs. However, this is not possible when there is an extreme mobility difference, such as that found in some III-V/germanium materials. In these cases, more success might result from expanding the device area out of the plane, since faster channels are restricted to the vertical gate-all-around architecture.

When considering all the options for the choice of material and architecture, high on the wish list is a steep subthreshold slope, because this enables substantial reductions in the supply voltage and the power consumption. With modern LSI, there are inherent issues associated with increases in power consumption, and they are exacerbated as transistor density increases. The underlying cause is that electrons and holes follow the Boltzmann distribution. This physical law dictates that the minimum value for the sub-threshold slope, which determines the supply voltage for the FETs, is about 60 mV/decade at room temperature (the sub-threshold slope is equal to 2.3 k_βT/q, where k_β is the Boltzmann constant, T is the temperature, and q the elementary charge). With the lower limit for the sub-threshold slope pegged at 60 mV/decade, the power consumption for the ICs has to increase as the integration density increases.

Fortunately, there is a way to overcome this limitation. What’s needed is to switch to a device that operates on non-thermionic processes, as they are not governed by the Boltzmann distribution of carriers. Operation of such devices may be based on quantum tunnelling, impact ionization, negative-capacitance, or mechanical vibrations. With any of these switching mechanisms the sub-threshold slope can be far steeper than 60 mV/decade.

A history lesson
Back in the late 1980s, Japanese engineer Fujio Masouka and his co-workers, working at Toshiba, invented the first vertical gate-all-around FET. Masouka, incidentally also the inventor of NAND flash memory, referred to this device as the surrounding-gate transistor. Whatever its name, it is a device that that will change the integration paradigm. Right now, all electronics devices used in our daily lives are based on the electronics of the 1960s. While deviating from this is certainly challenging, it has to happen, with a shift to the designs shown in Table 1. It is a change that is certainly feasible, since flash memory already uses a type of vertical gate-all-around architecture.

Our view is that all the alternative technologies overviewed in Figure 1 need to be mutually developed to realize a wearable, augmented-reality device with a high-performance computing system. We expect that heterogeneous direct integration of III-V nanowires on silicon and vertical gate-all-around tunnel FETs will both play an important role in this development, because nanowires with a tunnel III-V/silicon junction can include all of the technologies shown in Figure 1. A key attribute of TFETs that comprise all these technologies is that they have a much lower sub-threshold swing, allowing the supply voltage to plummet to just 0.2 V.

Table 1. Comparison of conventional wearable devices. The device performance and functionality refers to values of RAM memory. Performance per volume rapidly decreases. The performance ratio is the fraction of the performance per volume compared with that of a smartphone.

For TFETs, the steepness of the sub-threshold slope strongly depends on the bias condition. Apply a high internal electrical field to the tunnel junction and the addition of a smaller bias realises a steep sub-threshold slope. Thus, by taking care of the series resistance in the TFET, a steep sub-threshold slope may be realised. Alternatively, this can be engineered by combining a moderate tunnel junction with materials with precisely controlled doping and gate stacking technology. The latter approach is the one we have pursued.

Figure 1. There are alternative technologies for conventional CMOS; FET structures, channel materials, switching mechanisms, and integration schemes. Included is an illustration of switching curves by introducing alternative technologies.

One of the challenges with the TFET is ensuring a high enough on-current. As its value is determined by the tunnelling probability, this current depends on junction material characteristics, such as energy gap, effective mass and screening tunnelling length.

We have targeted a high on-current and a low sub-threshold slope when developing our devices. The design that we have trailblazed is a vertical gate-all-around TFET with a vertical InGaAs nanowire/silicon heterojunction and modulation-doped, core-multishell nanowire heterostructure. Selective-area growth is used to form this transistor.

There is much merit with our design. There is a staggered type-II band discontinuity at the n-InGaAs nanowire/p-silicon junction that aids TFET operation. What’s more, the vertical gate-all-around structure of the grown nanowire channels only modulates the potential of the InGaAs nanowire-edge – degeneration of the p-silicon is neglected, resulting in potentially good electrostatic gate control, key to obtaining a steep sub-threshold swing. Yet another asset of our architecture is that the two-dimensional electron gas that is generated by our core-multishell structure increases carrier concentration and tunnelling probability at the nanowire/silicon junction, and ultimately boosts our on-current.

A representative growth by our team results in vertically integrated nanowires on silicon, based on InGaAs/InP/InAlAs/δ-doped InAlAs/InAlAs/InP core-multishell layers (see Figure 2). Within these structures, there is a core In_0.8Ga_0.2As nanowire-channel with a: 200 nm-long, nearly intrinsic a zinc-pulsed doped layer; a 400 nm-long part with a silicon-doped layer; and a 600 nm-long part, heavily doped with tin. We use this axial junction to adjust the series resistance in the nanowire-channel, and to induce a large internal electric field under low bias. The thicknesses of the InP, InAlAs, δ-doped InAlAs, InAlAs, and InP capping layers are about 2.5 nm, 1.0 nm, 1.0 nm, 1.0 nm and 3.0 nm, respectively. Those values indicate that in these heterostructures fine 3D nanostructures can be precisely controlled on the atomic layer scale by selective-area growth. Critical to device performance is the inclusion of the inner InP shell layer, which facilitates the combination of a two-dimensional electron gas and quantum tunnelling.

Figure 2. (top left) The structure of vertical III-V nanowires on silicon, formed by direct growth. (middle and bottom) Energy-dispersive X-ray microscopy elemental mapping of nanowires composed of an InGaAs/InP/InAlAs/InP core-multishell structure.

The structure of our vertical gate-all-around TFET has been fabricated with a 3D device process flow, using a low-κ polymer resin, known as BCB (see Figure 3). Wrapping around the sidewalls of the nanowire-channel are a gate oxide, HfAlO composite oxide and tungsten gate metal, all added by atomic layer deposition. We have imaged this structure with scanning electron microscopy, after the reactive-ion process, and can see the core InGaAs nanowire on top of the nanowire channel.

The next step in our fabrication process is to form a Ni-InGaAs alloy contact with a small contact resistance to the core tin-doped InGaAs nanowire. After forming the Ni-InGaAs alloy layer, we deposit a drain of Ti/Au on top of the nanowire channel.

Figure 3. The vertical gate-all-around TFET structure has a core-multishell and a modulation-doping structure. A scanning-electron microscopy image shows the representative device structure formed using a 3D device process.

Delivering the promises
To assess the performance of our transistors, we have used a standard setup – a Keysight B1500A or 4156C, with a SMU cable – in a shielded box. Values reported for the current are normalized by the outer perimeter of the core nanowire, which is around 100 nm.

Measurements on our TFETs reveal a steep sub-threshold slope, with a minimum value of just 21 mV/decade (see Figure 4). The gate voltage window for the digital switch is 0.3 V, which is about one third of that of a modern FET. The current region where there is a steep sub-threshold slope extends over around four decades, while the average value for this key characteristic is 40 mV/decade.

Figure 4. Device performance of the vertical gate-all-around TFET. ID-VG curve shows a steep sub-threshold slope (the minimum sub-threshold slope is 21 mV/dec.) and high ION. The blue bar in this graph is V_DD = ~0.30 V. The I_D-V_D curve exhibits unique output properties. The sub-threshold slope vs I_D indicates a steep sub-threshold slope region in the range of about four decades, and a high I60. Transconductance efficiency is much higher than the physical limitation of conventional MOSFETs.

The currents produced by our devices are very encouraging. At a 0.5 V supply voltage, the on-current reaches 2.4 mA/μm – that’s a hundred times higher than that for a InGaAs/InP core-shell nanowire/silicon-based vertical gate-all-around TFET. With that design, the core-shell nanowire induces strain inside the core InGaAs nanowire, leading to a slight increase in on-current. Our core-multishell nanowire has the same strain effect, but a far larger current enhancement, thanks to the two-dimensional electron gas in the nanowire channel. The current at a sub-threshold slope of 60 mV/decade is 0.24 μA/mm, which is a thousand times higher than that of the core-shell nanowire/silicon-based vertical gate-all-around TFET.

Plotting the output properties of our devices reveals a unique curve, with a saturation region at a drain-source voltage of around 0.10 V. Insertion of an intrinsically doped InGaAs nanowire segment leads to an absence of the negative-differential resistance, sometimes observed in TFETs, when our device is operated under a negative drain-source voltage (that is a forward bias against p-silicon/i-InGaAs nanowire/n-InGaAs nanowire). A Kane model’s plot shows that the dominant transport mechanism is based on tunnelling.

Another strength of our TFETs is their exceptional transconductance efficiency, which is defined as the transconductance, divided by the drive current. This metric is a measure of the efficiency of the current drive in the ICs. For our devices, its value exceeds the physical limitation of the MOSFET, which is restricted to no more than 38.5 /V. For conventional FETs, this efficiency is virtually zero in the low-current region, while our vertical gate-all-around TFET exceeds this limitation over a wide current range. Transconductance efficiency peaks at around 520 /V at a drain source voltage of 0.25 V.

Note that it is not important that the maximum efficiency is high. Instead, what matters is that this efficiency exceeds the limits of the silicon FET over a wide range of low-current levels. When vertical gate-all-around TFETs are configured with a sufficiently high level of parallelism, there is no longer the need to pursue planar integration of the silicon FETs to try and improve performance as volume decreases (the requirement discussed in Table 1). The vertical gate-all-around TFET is also far better at thermal dissipation.

One other attribute of our TFETs is that, without a change in configuration, they can show p-channel behaviour with a steep sub-threshold swing. We need to look into this device mechanism in more detail, but preliminary investigations show that inverting the ground terminal results in a p-channel switch. The encouraging implication is that by simply aligning the vertical nanowires, a CMOS architecture can be constructed by forming interconnections for the ground terminals.

We have developed the integration of devices based on vertical III-V nanowires on silicon step by step; we began with nanowire HEMTs, nearly a decade ago, and now we have moved on to TFETs with a vertical gate-all-around architecture. We view these technologies as a continuation of Masuoka’s invention that will lead to the next true 3D integration scheme, taking us away from today’s planar integration devices, which have their roots in the 1960s. The vertical III-V architectures that we are pioneering accommodates co-integration and hybrid integration schemes. We are standing on the edge of a technology that will open up a new era, lasting for possibly the next 60 years.

Further reading
XK. Tomioka et al. Nature 488 189 (2012)
K. Tomioka et al IEEE IEDM Tech. Dig. 429 (2020)