New micro-textured film enables universal bare die carriers
Moving singulated die within production
environments can pose many challenges. While safe transport solutions
aplenty exist, all involve either tape and reel single use systems or
they employ carriers that are customized for each die size, a different
carrier for each and every form factor a fab produces. Delphon division
Gel-Pak has a new solution that is set to change how manufacturers
handle and test die in HVM settings.
By Raj Varma, CTO, Delphon
The emerging chiplet trend, which calls for the disaggregation of large monolithic functionality into interconnected smaller dies, offers significant advantages over the alternative system on chip (SoC). The move toward this technology has accentuated the need for known good die (KGD) that have been fully tested prior to integration into their final packaging. One challenge the industry faces in the test and assembly process is that conventional methods for handling chips can be problematic. A multitude of device dimensions and the need to pick and repick components or move them between processes calls for a more simplified way of handling these chiplets.
There is a need in the industry for a universal carrier to sidestep the need for molded trays with custom-designed pockets or carrier tapes that are only suitable for one-time use. Gel-Pak fills this gap with its well-known Vacuum Release™ tray technology, and most recently with a newly developed micro-textured film that can readily grip bare die without the need for pockets.
The material is inspired by the bio-based dry adhesion found in nature with geckos, lizards, beetles, spiders, and ants. This article discusses
Gel-Pak’s process around developing the ideal textures, fabrication process, and geometric patterns for this novel material, as well as its efficacy as an integrated circuit (IC) carrier.
Dicing films, JEDEC trays, and tape and reel are the commonly used device-handling formats.
Chiplets, Known Good Die, and Singulated Die Testing (SDT)
The modern semiconductor industry has faced major hurdles with the plateau of Moore’s Law. It is no longer the case that transistor geometries decrease to allow for the transistor density to double every two years. This has made the goal of packing in more processing capability per unit area much more difficult to achieve – monolithic chips are growing in physical size with the attempt to fit more hardware blocks onto a piece of silicon.
There is, however, a limit to how much can be integrated into a single die. Chiplets involve the 2.5D and 3D stacking of interconnected smaller dies (chiplets) with a well-defined subset of functionality. Compared to the monolithic chip, the high amount of integration allows for more silicon with which to add transistors without taking up additional space.
There is one major factor to consider when assembling chiplets: the integrity of the chiplets themselves. One “bad” die would result in a malfunctioning 2.5D or 3D module, leading to a poor yield. This potential downside has accentuated the need for KGD, where individual dies are tested prior to installation into the larger design. The employment of “good” die allows manufacturers to readily integrate these bare chips into the final package, dramatically improving the yield of these modules.
The test and assembly process for chiplet technology often requires banking and kitting of these components prior to final integration. Components are commonly moved within a facility for die level testing or processing. Changing device dimensions require component carriers that can adapt quickly to the rapid changes in form factor but still maintain the JEDEC standards to fit with existing equipment and pick-and-place (PnP) tools.
Wafer probe testing versus SDT
The conventional approach of testing individual die on a wafer is the wafer probe testing (WPT) method, or the wafer-level burn-in (WLBI). In this method, a specialized wafer prober with thousands of probing needles makes contact with the micro bumps on the bare die. However, it’s not a full and accurate test, because the presence of the surrounding die reduces testing accuracy and militates against running certain tests, such as high-current tests. Although drain and gate leakage tests (such as IDSS and IGSS) may be performed at WPT, the measured leakage values will change after singulation. Furthermore, defects such as side-wall cracks can bring additional changes.
Singulated die testing (SDT) allows for much more accurate results, with the resulting test parameters lining up with the packaged part. With these tests there is a much more thorough assessment of the reliability of the bare die. This allows vendors to effectively bypass the potential hurdle of integrating “bad” die that do not match the parameters necessary to meet the performance requirements of the chiplet.
The challenges of handling bare die during SDT
Singulated die testing presents a significant challenge, as bare die can be brittle and susceptible to particle contamination, cracking, and breaking. Ideally, a bare die carrier would allow manufacturers to pick and repick chips, access its sides, handle chips of different sizes, and immobilize the chip (See Table 1).
Some common methods for handling bare die include:
Φ Waffle pack chip trays
Φ Tape and reel
Φ Sticky tapes (dicing tape)
Waffle pack chip trays are often used to ship and carry bare die in a series of parallel cavities or pockets that hold semiconductor chips. The width, length, and positioning of the pockets are custom-tailored for a specific IC dimension. However, waffle pack trays cannot be reused in the event that there is a redesign or the vendor desires to ship another batch of ICs in which the chip dimensions have changed. These trays also do not allow for access to the edges of the chip, which is critical for devices with large stay-out zones. Additionally, these trays are not well-suited for the handling of thin die. There is always the potential for chips flipping in their pocket and die migration if the pockets themselves exhibit poor flatness tolerances.
Tape and reel packaging faces similar challenges; the requirement for customized pocket dimensions will not suffice for ICs that change form factor in a new design iteration. Because the pockets are sealed with a cover tape, which can only be removed once, the tape and reel packaging does not lend itself to the repick required for SDT.
Sticky tapes do not share the burden of customizing pocket dimensions to hold a particular IC as do both waffle packs and tape and reel packages. These tapes also allow access to the sides of the chip and immobilize the chip to prevent die migration. However, once a device is picked, it can never be put back to be reused, thus mitigating its utility for SDT.
Figure 2: Images of the adhesion system of various animal taxa. [Image Credit: [1 ]
Reversible adhesion in nature
Gel-Pak noted this need for a universal chip carrier that does not require custom compartments to hold the IC in place, allows for repicking, enables access to the edges of the chip, and immobilizes the chip itself. The inspiration for this reversible adhesion came from the dry adhesive characteristic found in nature. The ability of certain lizards, insects, and frogs to climb up walls and easily detach themselves is enabled by the micro-texturing of their toe pads. The toe pads consist of fibrillar micro- and nanostructures that conform to surface irregularities; the adhesion comes from the viscoelastic response of their outer membrane. As shown in Figure 2, each species exhibits a unique texture in which individual micro- and nanoscale fibers are adequately long and flexible to reach into the microscopic valleys of the surface they attach themselves to. In other words, these toe pads feature a dense array of microscopic contact points that demonstrate surface forces and kinetics to produce strong, controllable, and reliable adhesive contact. This interplay of surface texture and viscoelastic response of tissue materials is referred to as dry adhesive.
Developing the Novel Micro-textured Material
In the field of pressure-sensitive adhesives, micro-texturing has led to dry adhesion that enables a strong bond with a simple and clean release. Gel-Pak utilized the same textured adhesive concept in developing carrier tray technology by carefully researching other successful adhesive developments. One main parameter to observe in this process is the pull-off force, or the amount of force required to pull the adhesive off of the surface. This inevitably varies with preload, the compressive force placed upon the adhesive prior to pull-off. It has been shown that the pull-off force generally increases with preload, regardless of which geometric pattern the tip of the fibrils takes on (e.g., spherical, flat with rounded edge, mushroom, spatula, concave, square, dimples) [2] [3].
Moreover, a larger fibril will require more preload strength to obtain adhesion — and, as a result, more pull-off force to remove the material from the surface. In other words, the more force placed upon the viscoelastic membrane, the stronger the adhesion; and the thicker the fibrils, the more force required to attach and detach the material. This is relevant to better understand whether or not a PnP machine can gently lift the bare die from the carrier tray.
Gel-Pak focused on textures that were compatible with high-volume manufacturing (HVM). In HVM, conventional plastic fabrication processes such as injection molding and extrusion are used. Typically in plastics fabrication processes, texturization is primarily used for ergonomic considerations. However, this application necessitated the engineering of tack, or adhesion. Furthermore, the injection molding of textured adhesives is not generally practiced in the industry. During the process of developing this micro-textured material, Gel-Pak innovated an injection-molding textured adhesive that allows for HVM. There is no precedent for this in the plastics manufacturing industry, and the application itself is unique. As a result, ASTM and other test standards don’t have any tack metrology for textured surfaces. With the goal to use materials best suited for such processes, Gel-Pak tried six different texture geometries and more than two dozen different adhesive formulations. Eventually, this process was narrowed down to the staggered dimple (Figure 3).
Figure 3: Staggered dimple tip geometry used for the Gel-Pak’s novel universal carrier.
Testing the IC tray technology
After the process of selecting the texture geometry, various elastomers were used to generate a wide range of preload force curves (Figure 4). In this research initiative, the micro-texture features were not as small as in some of the previously published works; however, a wide preload force spectrum was enveloped by leveraging different adhesive chemistries. The prototype leveraged a custom-made flat JEDEC tray with the micro-textured film laminated to the surface (Figure 5). While JEDEC trays are really leveraged for packaged components, using the JEDEC form factor allowed for tests with common PnP machines, making this a more practical solution for SDT.
Each adhesive option was screened based on the following:
Φ Surviving shock/vibration/drop at -10oC, 20oC, and 50oC
Φ Long-term tack growth
Φ IC backside residue
Φ PnP and surface mount technology (SMT) pickability
After this testing, three different tack levels were finalized:
Φ Low tack
Φ Medium tack
Φ High tack
Figure 4: Pre-load versus pull-off force for six different elastomer chemistries.
The low-tack material corresponds to elastomer 6 in Figure 4. This grade of adhesion is ideal for in-process device handling, such as testing. The medium tack, or elastomers 2, 3, and 4, is preferred for in-process handling as well as shipment. High tack, or elastomer 5, would be ideal for more robust packaged devices such as quad-flat no-lead (QFN) packages. Finally, we tested the resulting three micro-textured materials on several different PnP machines, including the Royce, Besi, Muhlbauer, and MRSI, as well as the Juki Surface Mount Technology System. With only a few modifications to the equipment parameters, all the machines were able to successfully pick up the sample IC devices from the modified trays at moderate unit per hour (UPH) rates. The modifications allowed just enough z-axis down force to seal the vacuum cup with the device surface, pull the vacuum to an optimum threshold, and initiate the pick.
Figure 5: Image of the micro-textured film laminated to the flat JEDEC
tray to allow for the adhesion and immobilization of bare die of
different sizes.
Conclusion
Gel-Pak’s textured universal chip carrier is built upon innovation in both material science and manufacturing technology. We explored both the bump geometry and elastomer materials to ensure that components strongly adhere to the material’s surface with minimal effort and can be easily removed via PnP and SMT machines. The carrier is best suited for singulated die tests for KGD.
