Cadence Expands Collaboration with Samsung Foundry
Cadence Design Systems, a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE), has announced that it has expanded its collaboration with Samsung Foundry to accelerate 3D-IC design. Through the continued collaboration, the reference flow featuring the Cadence Integrity 3D-IC platform has been enabled to advance Samsung Foundry’s 3D-IC methodology. Using the Cadence platform, customers creating complex, next-generation hyperscale computing, mobile, automotive and AI applications can greatly optimize power, performance and area (PPA) for each die.
The PPA of a design can be impacted when chips are stacked
in a 3D-IC configuration versus a 2D configuration due to the presence of large
3D structures like TSVs, which connect the stacked chips. In addition to
blocking standard cell placement area, these structures block routing resources
as well. The Cadence Integrity 3D-IC platform alleviates these traditional challenges,
letting users create multiple TSV insertion scenarios and devise an optimal 3D
structure placement on a die with reduced wirelength penalties while boosting
PPA and productivity. The platform also lets users perform 3D-IC design
planning, implementation and signoff from a single cockpit, making the design
process faster and easier.
