News Article
Process Development
Infineon Technologies and Micron Technology have released the complete
specification for their reduced latency DRAM II (RLDRAM II) architecture.
Infineon and Micron co-developed the RLDRAM architecture to ensure
standardisation, multi-sourcing, and functional compatibility.
Infineon Technologies and Micron Technology have released the complete
specification for their reduced latency DRAM II (RLDRAM II) architecture.
Infineon and Micron co-developed the RLDRAM architecture to ensure
standardisation, multi-sourcing, and functional compatibility.
RLDRAM II products will operate at speeds of up to 400MHz. The devices will
be the second-generation for the companies ultra high-speed double data
rate (DDR) SDRAM combining fast random access with extremely high bandwidth
and high density. Target applications are communications up to 40Gbits/sec
and data storage applications. Datasheets for the 288Mbit RLDRAM II devices
are now available.
The RLDRAM II boasts a low latency and random cycle time (tRC) of 20ns
providing a higher data throughput. Additional advantages of the RLDRAM II
feature set include; on-die termination (ODT), multiplexed or
non-multiplexed addressing, on-chip delay lock loop (DLL), common or
separate I/O and programmable output impedance and a power efficient 1.8V
core.
The devices are available in a standard 144-ball FBGA, 11x18.5mm packages.
specification for their reduced latency DRAM II (RLDRAM II) architecture.
Infineon and Micron co-developed the RLDRAM architecture to ensure
standardisation, multi-sourcing, and functional compatibility.
RLDRAM II products will operate at speeds of up to 400MHz. The devices will
be the second-generation for the companies ultra high-speed double data
rate (DDR) SDRAM combining fast random access with extremely high bandwidth
and high density. Target applications are communications up to 40Gbits/sec
and data storage applications. Datasheets for the 288Mbit RLDRAM II devices
are now available.
The RLDRAM II boasts a low latency and random cycle time (tRC) of 20ns
providing a higher data throughput. Additional advantages of the RLDRAM II
feature set include; on-die termination (ODT), multiplexed or
non-multiplexed addressing, on-chip delay lock loop (DLL), common or
separate I/O and programmable output impedance and a power efficient 1.8V
core.
The devices are available in a standard 144-ball FBGA, 11x18.5mm packages.

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