Infineon Opens Up Yellow Brick Road
The researchers have shrunk will present film thicknesses into nanotechnology geometries. The results show that thin barrier films, key components for advanced copper chip wiring, will meet the electrical and functional demands defined for the end of the International Technology Roadmap for Semiconductors (ITRS), which extends to 2016. The ITRS expects a reduction of the barrier thickness from 12nm (100nm node, 2003) to 2.5nm (22nm node, 2016).
Hermetic encapsulation of copper lines has to prevent copper diffusion into the dielectric isolation, and in particular from reaching the transistors below the wiring layers in the chip. If copper migrates into the transistor level, it destroys device operation.
To achieve best chip performance, these barrier films have to be processed as thin as possible for two reasons. First, ultrathin barrier films allow more room for conducting copper, lowering resistance. Second, current flow must cross the barrier film in the vertical interconnects between the layers of copper wires (via holes), so an ultrathin film lowers this electrical resistance, too.
The results obtained demonstrated barrier functionality against copper diffusion with film thicknesses of less than 2nm, meeting the same stringent reliability requirements as the 50nm thick barrier films used in current semiconductor products. The electrical resistance of via holes with such thin barrier films is sufficiently low to realise such structures in the high-speed microprocessor chips expected to come to production by the middle of the next decade.
The manufacturing tools needed for the fabrication of chip generations in the timeframe beyond 2010 do not yet exist. The researchers extended the processes in existing manufacturing tools far beyond their use for todays products. This allowed the reliable deposition of thin contiguous functional films with sub-2nm thicknesses as required. The results therefore also demonstrate that the use of state-of-the-art thin film deposition techniques may be extended for future chip generations rather than requiring new atomic layer deposition techniques.
The copper wires were fabricated with the damascene metallisation technique. In this technique, grooves and holes are filled by deposition of metal followed by a complete removal of all metal covering the filled structures by chemical mechanical polishing. "Damascene" refers to the ancient ornamentation technique used in damascene swords and still a major jewellery production method.
The silicon wafers used for the electrical assessment of the embedded copper lines were processed with standard semiconductor manufacturing equipment and processes developed in Infineons Munich cleanrooms.
Infineon believes it has converted a red brick ("manufacturable solutions are NOT known") in the ITRS to "manufacturable solutions are known" (yellow brick). The company therefore expects that the next edition of the ITRS will be updated accordingly.
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