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Copper And Low-k At Volume

Motorola reports its first volume shipments of microprocessors produced using a low-k insulating dielectric during its copper metallisation process on 200mm wafers.

Motorola has applied this process to PowerPC microprocessor
products including the G4 PowerPC processor and the MPC 7455 and 7457
devices. The products run up to 20% faster and at lower power than those
made without it while maintaining high yields and reliability.


Scientists from Motorolas DigitalDNA Laboratories in Austin, Texas
originally developed the low-k process at the 0.13micron technology node.


The process was reverse transferred into a high performance 0.18micron
silicon-on-insulator (SOI) process for immediate product shipments. Motorola
has been shipping products manufactured at the 0.18 micron SOI process since
Q1 2003 and plans to ship at 0.13 micron later this year. Motorola has been
shipping SOI products in volume since Q4 2001.


Dr Suresh Venkatesan, director of CMOS Development in the Digital DNA
Laboratories, gives further details: "The process utilizes a hydrogenated
silicon oxycarbide (SICOH) film."



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