VLSI Symposium, Kyoto, Japan
Toshiba has developed and verified the operability of a memory cell
technology for embedded DRAM system LSIs on silicon-on-insulator (SOI)
wafers, claimed as a world first. Toshiba aims to apply the new technology
to mass production of system LSIs for broadband network applications in
2006. Toshiba has experimentally fabricated a 96kbit cell array.
Toshiba succeeded in forming embedded DRAM system LSI on an SOI wafer by
developing a new DRAM memory cell technology that makes use of the
characteristics of SOI wafer itself, eliminating the necessity of capacitors
where current DRAM cells store data. The new memory cell technology, dubbed
floating body cell (FBC), will be used for embedded DRAM system LSI for the
45nm generation on at Toshiba.
A conventional DRAM cell consists of a capacitor, where electric charge is
stored, and a transistor that functions as a switch. The newly developed FBC
does not have a capacitor and memorises data by storing the electric charge
in the transistor. Since the transistor works as both capacitor and electric
switch, the cell area is half that of a conventional DRAM cell.
Compatibility between the manufacturing processes of DRAM cells and logic
ICs is a crucial issue for the development of embedded DRAM cell technology
for SOI-based system LSIs. For full compatibility without any degradation in
performance, a poly-Si plug - a buffer layer of poly-silicon - is formed in
the contact area of the memory cell.
Toshibas experimental 96kbit cell array achieved successful operation in
all bits, a 36nsec access time, a 30nsec data switching time, and a 500msec
data retention time (at 85C). These results demonstrated to Toshiba that the
new FBC technology could be applied to system LSIs integrating DRAM cells
with Mbit or greater memory capacity.
Toshiba has developed a new gate dielectric for use on its future 65nm CMOS
process technology. The company says that it has developed a CMOS transistor
that reduces gate leakage current to a thousandth of that of conventional
gate dielectrics. The company replaced the usual silicon dioxide with
nitrided hafnium silicate (HfSiON), a high dielectric constant (high-k)
material. Toshiba now plans to apply the new process to the mass production
of system large-scale integration ICs (LSIs) for mobile products in 2005.
The performance of the HfSiON gate dielectric film was confirmed with an
experimentally fabricated LSI with 50nm gate-length CMOS transistors and an
equivalent oxide thickness (EOT) of 1.2nm. Sub-threshold characteristics
demonstrate currents of 650microA/um and 250microA/um for the n- and
p-MOSFETs, respectively.
The gate dielectric has to endure processes at temperatures at up to 1000C.
Toshibas HfSiON gate dielectric formed by plasma nitridation demonstrated
high thermal durability at up to 1050C without phase-separation or
crystallisation.
Intel is looking to tri-gate fully-depleted transistors for its shrink
efforts down to gate lengths of 30nm. The companys scientists described how
the device turns on at lower voltages and that by using a spacer printing
technique the drive current was increased 1.2 times on a planar device for a
given width.
The team also found that the tri-gate body dimensions are flexible and
relaxed compared to single- and double-gate approaches. Experimental devices
have been produced at Intels 300mm Fab D1C in Oregon.
Other teams from Intel described work on radio components produced on
0.18micron CMOS processes. One presented 10GHz, 20mW, fast-locking, adaptive
gain phase-locked loops (PLLs). A deep n-well isolation was used to separate
the analogue from the digital circuits. Also from a 0.18micron CMOS process,
Intel workers succeeded in producing a 5GHz quadrature voltage controlled
oscillator (VCO).
UMC presented its strained silicon technology using wafers built on
AmberWaves substrate technology. The company reported that the process
exhibits a significant CMOS performance enhancement with over 20% current
driving capability successfully demonstrated on a 70nm strained silicon
transistor with a speed enhancement of over 10% on a test circuit.
SW Sun, vice president of UMCs Central Research and Development division,
says: "UMCs strained silicon process offers an alternative path to realise
performance improvements without aggressive gate length shrinkage. We
believe that many of our foundry partners will benefit from this enabling
technology in the future. We are also working with AmberWave to enhance
p-channel transistor performance, improve strained layer defect density and
decrease substrate costs associated with this strained silicon technology."
AMD researchers presented detailed information on their creation of fast
transistors. The company claims some of the highest performance levels ever
published. One set of transistors uses fully-depleted silicon-on-insulator
(FDSOI) and metal gates. These deliver PMOS (P-channel metal-oxide
semiconductor) speeds with up to a 30% increase over previously published
transistors. Another set uses strained-silicon and metal gates to deliver
20-25% higher NMOS (N-channel metal-oxide semiconductor) performance
relative to conventional strained-silicon transistors. The companys metal
gates use nickel silicide.
Metal gates and FDSOI create transistors with significantly improved gate
conductance, appropriately engineered workfunction and enhanced carrier
mobility. Strained silicon further boosts carrier mobilities for the NMOS
devices.
Craig Sander, vice-president of process technology development, comments:
"Metal gate technologies provide a means to reduce the effective oxide
thickness and alleviate the stringent requirements imposed on aggressive
gate oxide scaling required for high performance transistors."
Currently, SOI transistors are built on a thin top-layer of pure silicon
that sits atop another layer of insulating oxide. The insulating layer
ensures that electrical current flows only through the thin top-layer of
silicon, and doesnt leak down into the material that forms the bulk of the
wafer. The thinness of the silicon top-layer contributes to better
transistor performance, in part because it minimises undesirable electrical
characteristics that could inhibit transistor operating efficiencies. Fully
depleted SOI, an advance over todays SOI technologies, could offer higher
performance capabilities thanks to a much thinner top-layer of silicon.
Strained-silicon transistors offer increased performance potential due to
the silicon atoms being "strained" to enhance carrier mobility, which
results in improved electrical current flow.
Toshiba and SanDisk have jointly developed a high density NAND flash
memory-cell structure that allows fabrication of 4Gbit NAND flash memory
using 90nm design rules.
The new memory cell has a physical cell area of only 0.041micron2 and
supports scaling to future generations of smaller feature design rules. The
two companies plan to employ the new NAND cell technology starting in H1
2004 with 2Gbit and 4Gbit NAND Flash memory chips. The devices will be
manufactured by the companies FlashVision Japan joint venture production
facility at Toshibas Yokkaichi operation in Japan.
In the new NAND memory cell structure, the floating gate is completely
self-aligned to the active area. This design characteristic supports scaling
of the structure for fabrication beyond the 90nm design rule and is expected
to provide a distinct advantage over the current NAND memory cell structure,
where further scaling below 110nm becomes difficult.
The new memory cell structure is designed to support both 2Gbit single-level
cells (SLC) with an area per bit of 0.041micron2 as well as 4Gbit
multi-level cells (MLC), which effectively will have an area per bit of only
0.0205micron2. The MLC structure allows each memory cell to carry two bits
of information, instead of one.
AngelTech Live III: Join us on 12 April 2021!
AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!
Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.
2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.
We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.
We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.
Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.
Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.
So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.
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