Process Development
The FeRAM offers
high-speed writing, low power consumption and the ability to preserve its
contents without electrical power. Shipment of samples for mobile electronic
devices is scheduled to start in August 2003.
Compared with conventional FeRAM on a 0.35micron CMOS process, the new
FeRAM-embedded SoCs have larger-capacity memory. Compared with Flash or
EEPROM (electrically erasable programmable read-only memory), the 0.18micron
FeRAM features higher reliability and a five-times faster processing speed,
an extended number of write cycles and complete data retention without
battery back-up.
The new development incorporated several novel technologies:
* a hydrogen-damage-free cell structure
* a stacked cell configuration that reduced the memory cell size to
one-tenth of previous models, and ultra-fine-ferroelectric capacitors under
100nm in thickness leading to a dramatic miniaturisation of the die size
* a record low power consumption during operation at only 1.1V
With a view to making its product as environmentally friendly as possible, a
lead-free SBT (SrBi2Ta2O9 or strontium-bismuth tantalate) is used for the
ultra-fine ferroelectric capacitors.
Tegal announced a new set of sputter process applications for its Sputtered
Films subsidiary's Endeavor-AT PVD cluster tool. Combined with the
introduction of the company's new MF-RF and DC-RF coupled S-Guns, the
processes are designed to deliver high quality reactive sputtering for a
variety of challenging electronic applications for the semiconductor
industry. The company sees major benefits for manufacturers of LED and
optoelectronic devices, power MOS producers and for the MEMS, SAW, and EUVL
photomask industries.
Reactive sputter deposition of dielectric films has historically suffered
from equipment and process anomalies that have, until now, resulted in
performance sacrifices when depositing materials like silicon nitride,
silicon dioxide and aluminium-based insulating films. The traditional
challenge of reactive sputter deposition has been to eliminate the chamber
arcing that inevitably results from the dielectric properties of the
deposited films themselves - while maintaining high deposition rates, tight
process stability and low cost of ownership. Previous measures to address
this challenge by other PVD tool suppliers have resulted in deposition rate
reductions with degraded yield from thermal and electrical damage to devices
during deposition.
IC packaging and test company Advanced Semiconductor Engineering (ASE) has
launched volume production of chip packages using Polymer Collar WLP - a
wafer level process licensed from Kulicke & Soffa Industries (K&S). ASE has
ramped up wafer-level-package production capacity of up to 10mn units per
month.
Polymer Collar packaging is an enhancement of K&S's Ultra CSP wafer-level
package technology which ASE has previously licensed in January of 2001. The
technology combines an epoxy-based carrier with flux agents to form a
polymer structure, or "collar," around the solder ball neck or chip-side
solder joint, increasing solder fatigue performance. During manufacturing,
addition of the Polymer Collar replaces the traditional fluxing step,
resulting in a simplified manufacturing solution.
Thermal cycling tests on the Polymer Collar Ultra CSP packages demonstrated
greater than 30%-50% increase in solder joint life compared with a standard
Ultra CSP.
Semiconductor assembly and test service provider Advanced Interconnect
Technologies (AIT) has licensed Flip Chip on Substrate (FCOS) package
technology from Advanpack Solutions (APS). AIT will gain rights to use APS'
proprietary pillar-bumping process. FCOS packaging can be used on high-pin
count, performance-driven devices such as microprocessors, ASIC, memory
chips and RF devices, that require operating frequencies that cannot be
achieved with standard wirebond packaging techniques.
The pillar-bumping interconnect technology uses perimeter or array flip-chip
pads to connect an integrated circuit (IC) to a substrate material. The APS
process starts by taking a die with pillar bumps attached to the I/O pads of
the IC. The pillar bumps are dipped in a flux material, flipped and mounted
on a PCB substrate and sent through a reflow oven. During reflow, the die is
simultaneously cured in place and electrically connected to contact pads on
the substrate. The packages can provide improved electrical and thermal
properties and a lower profile as compared with traditional wire bonding.
APS has also developed irregular-shaped pillar bumps to serve varying market
demands.
AIT will use pillar-bumping for its PBGA, FBGA, SIP and LGA packages.
Packages will be available for qualification in Q2 2004. AIT's FCOS packages
will also be available in a "lead free" version for customers who need to
meet the demand for "green" technologies.
AngelTech Live III: Join us on 12 April 2021!
AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!
Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.
2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.
We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.
We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.
Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.
Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.
So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.
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