Profit Control

The
two generic means of controlling gate CD are advanced
process control (APC) and process window management
(PWM). APC seeks to adjust process parameters inside
process windows. PWM seeks to align the process windows,
primarily by enabling recurrent equipment matching.
Both APC and PWM are evolutionary next-steps in the
“copy exact” philosophy of semiconductor manufacturing.

Advanced
process control

APC
is a closed-loop control system in which process correctables
are fed back to the preceding module or fed forward
to the next to reduce parametric variation on product
wafers. The success of APC is based on two assumptions:
the existence of an effective control model and the
existence of a valid process model (Figure 1). For an
effective control model, timely measurement data must
be supplied to allow high control gains to be used without
danger of overcorrecting (Figure 2). For the process
model to be valid, it must account for a useable fraction
of the observed variation and leave a minimum of unexplained
variation in the form of residuals.

Alternatively,
in the case of stand-alone CD and overlay metrology,
dramatic improvements in APC performance can be achieved
through optimising capacity and sample plans. For example,
increasing an overlay sample plan from four arbitrarily
selected fields to ten statistically optimised fields
may nearly double the potential effectiveness of OL
APC. The requisite metrology capacity pays for itself
by accelerating shrinks and enhancing profitability.

Process
window monitoring

PWM
is an open-loop control system in which multiple parameters
are monitored for the purpose of detecting excursions
and matching process equipment using monitor wafers.
PWM is a powerful tool for dealing with unexplained
intra-module or inter-module process variation that
can reduce performance of APC, particularly, since performance
gaps commonly arise from collapse and/or displacement
of process windows. As an example, Figure 4 shows litho
and etch CD windows as a function of litho defocus.
The optimal litho and etch windows are displaced by
0.2µm, creating a 30% etch-CD risk and the potential
for catastrophic yield loss. Most CD APC applications
are blind to this class of inter-module variation.

The
root-cause of etch window displacement may not be the
CDs themselves, but rather the resist sidewall angles
as they change through focus and erode during etch.
We expect that PWM will be most effective when embedded
in smart metrology tools that provide large amounts
of unique information.

In
addition to its role in supporting APC, PWM can be used
by itself as a fully automated, web-based monitor for
process tool stabilisation and tool matching across
entire areas. In lithography, CD PWM is implemented
using multiple focus-exposure matrices measured on a
scanning electron microscope (SEM) or scatterometry
(SCD) metrology tool (Figure 5). Automated analysis
of these matrices can generate dose, focus and depth-of-focus
metrics for each lithography cell and each critical
layer in a factory. Figures 6, 7 and 8 provide examples
of results from PWM for differing purposes. Figure 8
shows how PWM can exceed the capability of in-situ metrology.
Combining flash memory and foundry data from two different
factories, we observed a maximum focus tracking error
of 30nm without calibration. Our development work indicates
that, with calibration, the noise floor for CDSEM-PWM
system is less than 12nm at 30.

Problem
looms at 65nm

Currently, CD shrink entitlement is being held back
by poor correlation of traditional lot-based CD averages
to device yield - and yield entitlement is falling.
Shrinking design rules are narrowing the overall CD
process window, creating a looming CD-related yield
problem for the 65nm technology node. With the advent
of 300mm wafers and 130nm design rules, yield-affecting
CD control problems have shifted to the cross-wafer
and cross-field levels. This problem has contributed
to the delay of 130nm technology in the foundries. Going
forward, the International Technology Roadmap for Semiconductors
(ITRS 2001) has identified the 65nm technology generation
as a showstopper for gate CD control, with no known
solutions.

Nevertheless,
recent data has shown promising results for a scatterometry-based
process window monitor used for cross-field CD control
applications.

Cross-field
error is typically the largest systematic component
of variation. Much of this is correctable with a large
revenue impact. Calculations suggest that the weekly
added value of correcting these errors on a microprocessor
line with 1000 wafer starts per week could be as much
as $6.0 million from shrinks, $5.8 million from speed
enhancements and $2.9 million from extending the life
of 200mm fabs. Many CD errors are caused by cross-field
deviations in focus and dose (Figure 9). The long-term
scanner focus variation, as measured by PWM, can have
up to a 200nm range. By contrast, the long-term repeatability
of the PWM focus measurement is less than 10nm, meeting
the ITRS requirements for focus metrology at the 65nm
node.

Lost
shrink and speed binning opportunities currently result
in millions of dollars of lost revenue per year - and
the situation will get worse at 65nm. These losses will
be due primarily to shrinking process windows and persistent
cross-field variation. Scanner metrology will no longer
work at 65nm because focal tests have relatively poor
measurement precision and fail to provide simultaneous
dose and depth-of-focus information.

Fast
scatterometry-based process window monitors with 10nm
focal precision can provide a faster, cheaper, better
solution. PWM can be moved to inexpensive metrology
tools, liberating $20-30 million lithography cells for
wafer production.

In
addition, we expect traditional APC architectures to
be augmented at the 90nm node to support the precursors
of fully depleted silicon-on-insulator transistor technology
such as Intel’s Terahertz project. At the 90nm
node, physical gate lengths are expected to reach 50nm
and decrease rapidly to 30, 20, and 15nm in subsequent
generations. Some microprocessor manufacturers may fabricate
50nm gates at the 130nm node. Such design rules will
generate more rigorous process control requirements
for rapidly shrinking, overlapping process windows.
Ultimately APC architectures may be called upon to provide
comprehensive control of transistor formation. To address
the new requirements, APC architectures must incorporate:

• New
  metrology tools, measurement targets and analysis
  software to ensure that accurate, yield-relevant corrections
  are fed to the APC system. Examples are CD scatterometry
  and next-generation overlay tools that use grating
  targets to reduce measurement uncertainty and improve
  device correlation.

• Infrastructure
  extensions that enable seamless root-cause determination
  and correction when the APC history analysis generates
  an action request. Examples are model-based process
  window monitors (PWM), advanced equipment control
  (AEC), fault detection/classification (FDC), integrated
  diagnostic monitors, and internet-based support.

• Factory-wide
  open APC frameworks (such as KLA-Tencor’s Catalyst)
  that allow single-point manufacturing execution system
  (MES) integration and co-ordination of multiple APC
  applications running simultaneously in several process
  areas. Consider an L effective controller that feeds
  forward chemical mechanical planarisation (CMP) thickness
  data to correct CDs in litho, litho CD data to correct
  CDs in etch and etch CD data to correct L effective
  during spacer formation or ion implantation.

• Business
  rule management that supports high-mix production
  and multiple APC strategies. The simple APC business
  rules developed initially in low-mix microprocessor
  and DRAM factories must be extended to address high-mix
  manufacturing contexts in foundries and to support
  multiple strategies that require different levels
  of metrology and process tool dedication for low and
  high ASP products.

• Multi-threaded
  APC applications that respond to more than one input
  and generate more than one output. Consider a litho
  area that exhibits systematic cell-to-cell, lot-to-lot,
  wafer to-wafer, field-to-field and die-to-die CD variation
  that might be corrected by feeding back dose offsets
  for each cell, lot, wafer, field and die, respectively.

• High-bandwidth
  support for stand alone, clustered and integrated
  metrology tools. Stand-alone and 300mm cluster metrology
  tools generating data on a lot-to-lot basis will be
  joined by integrated metrology tools that generate
  data on a wafer-to wafer basis. In some cases, bandwidth
  requirements may force on-tool distillation of correctables
  required for lot-based recipe modification.

• Physical
  model-based process control that can predict electrical
  characteristics. APC applications will evolve from
  simple offset corrections (CD control) and empirical
  response surfaces (overlay control) to physical models
  that predict electrical characteristics such as effective
  gate length (L-effective) and equivalent oxide thickness
  (EOT).

• Control
  of transistor formation using models that predict
  device performance. Model-based process control will
  evolve from simple models to more sophisticated physical
  models using measurements from multiple tools to predict
  device performance characteristics such as voltage
  threshold (V-threshold), off current (I-off) and drive
  current (I-drive).

Fig.7:
A large overlap window is critical for manufacturing.
Here, PWM assists in determining the common lithographic
focus-exposure window over five positions in the scan
field. Overlap windows can be spatial, temporal, or
tool-to-tool

Ultimately,
driven by compelling economic forces, today’s APC,
AEC, FDC and PWM will evolve into a new species of process
control that we refer to as process window control.
PWC opens a vast array of possibilities. Gate stack
formation will take on new meaning as we force the overlap
of multivariate process windows from deposition to alignment,
exposure, etch, spacer formation and ion implantation.
Intra-field proximity effects in lithography may be
compensated for in the etch module by varying power,
pressure, flow and chemistry using feedback from embedded
measurement tools. Cross-wafer non uniformity induced
in the etch module may be corrected in lithography using
field to-field and intra-field dose control. Factors
that were once ignored in APC, such as lithographic
defocus or spacer sidewall angle, may become an integral
part of process correction as scatterometry proliferates.
APC, AEC, FDC and PWM will continue, but will function
more robustly inside the context of process window control.

Links
to gate CD control

align="justify"Gate
CD control is an eminent example of how process window
control can be used. Assuming constant yield, links
can be established between gate CD control, die-density,
average selling price and factory life extension.

Characterising
the variability of gate CD can be used to separate out
correctable systematic cell, lot, wafer, field, die
and site variation from lot-to-lot temporal variation.
Benefits accruing from improved CD control are contingent
upon a number of assumptions, including a price performance
premium, unsaturated market demand, scalability of interconnect
speed, dimensional scalability of other critical layers
and the relatively small incremental cost of PWM and
APC. Simple calculations can establish an expected entitlement
for maximum incremental return against which the actual
return on investment (ROI) may be compared.

The
Pareto chart in Figure 10 shows such examples of incremental
return due to microprocessor speed improvement, increase
of die density, factory life extension and rework reduction
assuming APC produces a 15% to 30% decrease in lot-to-lot
CD variation. Since the model for total CD variation
includes lot, wafer, field and site components, the
actual shrink ratios are only about 0.95 and 0.90, respectively.
Initial production is assumed to be 1000 wafers per
week, with 150 dies per wafer at $100 per die. These
entitlements assume that gate CD is the critical speed
and shrink bottleneck. We are not modelling the interactive
incremental return due to simultaneous increase of speed
and density.

Return
on investment can be increased dramatically by controlling
the other components of CD variation at the site, field
and wafer levels (Figure 3). The extension of APC to
more critical steps and layers could remove speed and
shrink bottlenecks in other parts of the process. Finally,
the effectiveness of the APC algorithm itself could
be improved by making changes in the manufacturing context
that minimise measurement delay and the contribution
of unexplained process variation.

Fig.9:
Process windows define the ranges of dose and focus
that create < 10% CD variation. Process windows will
shrink at 65nm

Fig.10:
Pareto of predicted incremental revenue due to microprocessor
speed improvement, increase of die density, factory
life extension, and rework reduction

Some
features of the future semiconductor production landscape
emerge:

• Economic
  considerations will drive demand for more granularity
  in parametric control.

• Control
  of module-to-module parametric window overlap will
  become a necessity as gate CD control merges with
  L-effective control.

• Far
  more effective and complex APC applications will appear
  as measurement and process delay times are reduced.

• Further
  reduction of unexplained variation will be accomplished
  using process window monitors, smart metrology tools
  and statistically optimised sample plans.

• Further
  reduction of delays will be accomplished by increasing
  the level of metrology integration, clustering and
  dedication.

In
difficult economic times, the metrology-driven shrink
may be the most cost-effective alternative to massive
investment in new process equipment or factories since
it both extends the life of current assets and provides
the foundation for higher returns during economic recovery.
Advanced process window control is a key enabler for
this strategy.