Motorola's 4Mbit MRAM
The chip is based on a 0.18micron five-level metal CMOS process technology. Motorola demonstrated 1Mbit MRAM using 0.60-micron technology in June 2002.
Motorola believes that MRAM could replace multiple memory devices with reduced system complexity, lower overall system cost, and improved performance.
Dr Claudine Simson, chief technology officer, Motorola's Semiconductor Products Sector, comments: "We've made significant progress toward establishing a solid MRAM manufacturing technology capability. We're now working with lead customers on performance refinements for future market introduction and broader sampling next year."
MRAM could initially enter the market in applications that require speed, reliability and low power, says Motorola.
Motorola has obtained several patents covering multiple aspects of the bit cell structure, programming method and circuit design.
The three most fundamental challenges facing MRAM implementation are bit selectivity, data retention and scaling. Motorola says that these are addressed by its technology.
. Improved bit selectivity allows the writing of information anywhere in the memory without disturbing previously stored data. Exceptional data retention allows stable, long-term storage of information. Scaling to smaller geometries allows designers to pack more cells into a smaller area, resulting in lower cost.
The memory uses unidirectional programming currents with isolated write and read paths and balanced current mirror sense amplifier. Motorola is scheduled to present details of its "toggle" approach to MRAM at the IEEE International Electron Devices Meeting (IEDM), December 8-10, 2003.
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