Arteris accelerates AI-driven silicon innovation
“In the chiplet era, the need for computational power increasingly exceeds what is available by traditional monolithic die designs,” said K. Charles Janac, president and CEO of Arteris. “Arteris is leading the transition into the chiplet era with standards-based, automated and silicon-proven solutions that enable seamless integration across IP cores, chiplets, and SoCs.”
Moore’s Law, predicting the doubling of transistor count on a chip every two years, is slowing down. As the semiconductor industry accelerates efforts to increase performance and efficiency, especially driven by AI workloads, architectural innovation through multi-die systems has become critical. Arteris’ expanded multi-die solution addresses this shift with a suite of enhanced technologies that are purpose-built for scalable and faster time-to-silicon, high-performance computing, and automotive-grade mission-critical designs.
Business Impact: From Innovation to Market Acceleration
Arteris’ offering reduces chiplet and SoC design time, along with the optimization of power, performance, and area bottlenecks by providing key Network-on-Chip (NoC) IP technology for standardized die-to-die communication and automating key SoC creation workflows.
Built for interoperability, the expanded solution supports the Universal Chiplet Interconnect Express (UCIe) specification, various Arm AMBA protocols, PCIe, and integration with leading physical IPs to ensure robust, standards-based ecosystem compatibility. Integration with products from major EDA and foundry partners — Cadence, Synopsys and global fabs — ensures a ready-to-deploy solution for silicon innovators and system companies creating electronics.
Key Capabilities of the Arteris Multi-Die Solution:
Silicon-proven non-coherent FlexNoC IP supports the relevant standards and integrates with third-party commercially available die-to-die controllers and PHYs.
New cache-coherent Ncore NoC IP capabilities enabling seamless cache coherent reads and writes across multiple chiplets, making multi-die systems look like a single piece of silicon to application software programmers.
Optimized Magillem Connectivity automation for SoC assembly from IP and chiplets, reducing project risks associated with manual, error-prone integration tasks.
Optimized Magillem Registers automation for integrating hardware and software from system map definition to validation and documentation based on a single source of truth.
Strategic Momentum
As part of their focus on supporting chip architecture across the board, Arteris is collaborating with leading players across the silicon value chain to enable next-generation AI and automotive platforms:
Arm is collaborating with Arteris to enable an interoperable chiplet ecosystem via the recent AMBA CHI C2C specification and the ongoing support of mutual automotive semiconductor customers, Tier 1s and OEMs.
Cadence is collaborating with Arteris to enable customers to realize their chiplet ambitions through integrated, optimized, standards-compliant IP and EDA tool flows, delivering significant time-to-market acceleration while reducing development costs.
Renesas is leveraging Arteris multi-die technology in its R-Car Gen 5 SoC platform for advanced driver-assistance systems (ADAS) that integrate CPUs, AI-enabled NPU, IVI-enabled GPUs, and ability to further boost AI throughput via chiplet extensions.
RISC-V ecosystem partners like Andes, SiFive and Tenstorrent are working with Arteris in support of domain-specific IPs and chiplets.
Synopsys is collaborating with Arteris to enable fast integration with a portfolio of standards-compliant IP and EDA solutions for multi-die designs.
