Qnity advances AI packaging
Qnity has introduced an integrated materials platform for advanced 2.5D and 3D packaging, targeting fine-pitch interconnects, HBM, chiplets and emerging substrate architectures through metallization, bumping, dielectric and patterning technologies.
Qnity Electronics has introduced an integrated materials and process technology platform targeting the manufacturing challenges associated with next-generation 2.5D and 3D semiconductor packaging, including chiplet-based architectures, high-bandwidth memory (HBM) and advanced substrate technologies.
The platform brings together metallization, solder bumping, dielectric materials and fine-line patterning processes, addressing the increasing requirements for interconnect density, coplanarity, critical-dimension control and manufacturing yield as AI accelerator architectures become more complex.
Advanced packaging approaches such as Chip-on-Wafer-on-Substrate (CoWoS), Embedded Multi-die Interconnect Bridge (EMIB) and HBM require increasingly precise control of plated structures and interconnect geometry.
Qnity's portfolio supports SnAg micro-bumps, copper-to-copper direct and hybrid bonding, as well as high-resolution dielectric and patterning processes.
The company reports that its processes can support 2 µm line/space metallization while maintaining tight critical-dimension control and low defectivity.
For HBM and other fine-pitch applications, the company's solder plating technology is designed to provide controlled micro-bump formation and improved coplanarity across mixed-pitch structures.
Copper deposition technologies are also aimed at improving within-die uniformity and plating consistency, which become increasingly important as interconnect dimensions shrink and package architectures increase in scale.
The materials platform additionally addresses the dielectric and lithography requirements of advanced packaging. Thick dry-film photoresist technology is designed for high-aspect-ratio copper pillar formation and fine-feature patterning, while dry-film photo-imageable dielectric materials target fan-out panel-level packaging and advanced substrates.
Glass-core substrate applications are another focus, with the dielectric technology supporting through-glass via (TGV) filling and reliability requirements.
Such substrate architectures are attracting increasing interest as the semiconductor industry looks for higher-density interconnects and scalable packaging platforms capable of supporting larger and more complex AI systems.
The broader development reflects a shift toward greater integration between materials engineering and packaging process development.
As AI, chiplets, HBM and heterogeneous integration drive higher interconnect densities and increasingly three-dimensional structures, controlling dimensional uniformity, surface characteristics, coplanarity and defectivity across multiple process steps is becoming critical to achieving reliable high-volume manufacturing.
Qnity plans to present details of the platform at the Heterogeneous Integration Global Summit during SEMICON Taiwan 2026 on September 1.
