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Alliances

Chartered Semiconductor Manufacturing has signed a multi-year agreement to provide volume manufacturing for Infineon Technologies.

The manufacturing
agreement includes Infineon's OptiMOS technology with potential extension to
its CoolMOS process.



These processes are used to manufacture power MOSFETs with computer,
communications, consumer, industrial and automotive applications. The
OptiMOS process fits within the tooling capabilities of Chartered's Fab 2,
but involves significantly fewer masking layers than a typical CMOS process
flow. The price per wafer is accordingly lower than for usual CMOS products
run in Fab 2.



As part of its capacity extension plans, Infineon will initially transfer
its OptiMOS technology process to Fab 2 with qualification due by the end of
2003. Volume production is scheduled to ramp in 2004. As part of the
agreement, Chartered will also supply non-OptiMOS technologies to Infineon.



Feinfocus has expanded its membership with the Advanced Packaging &
Interconnect Alliance (ApiA) in order to investigate the importance of x-ray
inspection as the semiconductor industry shifts towards wafer-level and
system-on-chip packaging. The company believes that nanofocus and
nanotomography inspection criteria will become more vital as a result of
these wafer technology trends. Feinfocus will collaborate with other APiA
members on x-ray inspection technology.
The APiA is an alliance of equipment suppliers and process developers in the
advanced packaging and interconnect industries.



The Semiconductor Equipment Consortium for Advanced Packaging (SECAP) says
it has successfully installed a 300 mm wafer bumping and wafer-level
packaging (WLP) line at Unitive Semiconductor Taiwan (UST). The installed
integrated process equipment from the SECAP member companies will be used
for high-volume manufacturing. This is claimed as the first fully integrated
300mm electroplated wafer bumping line installed at a wafer level packaging
service provider for immediate high-volume production.



SECAP and Unitive agreed to install the 300mm wafer bumping line in July
2002. With the SECAP process installation complete, the 300mm line is now
available to customers and prospective customers of SECAP member companies
for equipment demonstrations and processing evaluation.



The SECAP line enables member companies to further optimise their equipment
for the integrated process flow of typical wafer bumping lines. SECAP is
neutral to all packaging technologies and welcomes the opportunity to work
with all manufactures. SECAP members provide process support, but do not
sell or license process technology. The consortium consists of Semitool,
Suss MicroTec, Image Technology, Matrix Integrated Systems, NEXX Systems,
EKRA, BTU International and the Frauhofer Institute for Reliability and
Microintegration (IZM).



Japanese company Asahi Glass and International Sematech agreed to
collaborate on developing advanced mask technology and materials for use in
EUV lithography.



Besides providing ISMT with advanced mask materials, Asahi also will send
scientists to work with ISMT technologists at the consortium's advanced R&D
facility at the University at Albany, New York.
Asahi's interest in advanced materials for mask applications started with
the development of modified fused silica substrate and hard and soft
pellicle materials for 157nm lithography several years ago.
Asahi Glass will use ISMT's tools at UAlbany to further technology
development for their own commercial manufacturing efforts. Earlier this
year, ISMT entered into a five-year strategic alliance with UAlbany to
develop EUV infrastructure for industry needs in 2007. The programme focuses
on defect-free masks and special resists.



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VIEW SESSIONS
DISCO's Completion Of New Building At Nagano Works Chino Plant
Cadence Announces $5M Endowment To Advance Research
ASML Reports €14.0 Billion Net Sales
Imec Demonstrates 20nm Pitch Line/Space Resist Imaging With High-NA EUV Interference Lithography
AP&S Expands Management At Beginning Of 2021
GOODFELLOW Confirms Membership In The BSI UK Graphene Group
U.S. Department Of Defense Partners With GLOBALFOUNDRIES To Manufacture Secure Chips At Fab 8
ITRI And DuPont Inaugurate Semiconductor Materials Lab
Can New Advances In CMOS Replace SCMOS Sensors In Biomedical Applications?
SUSS MicroTec Opens New Production Facility In Taiwan
Panasonic Microelectronics Web Seminar
Will Future Soldiers Be Made Of Semiconductor?
Belgian Initiative For AI Lung Scan Analysis In Fight Against COVID-19 Goes European
Siemens And ASE Enable Next-generation High Density Advanced Package Designs
Onto Innovation Announces New Inspection Platform
Tescan And 3D-Micromac Collaborate To Increase The Efficiency Of Failure Analysis Workflows
Tower Semiconductor Announced Program Creating An Integrated-Laser-on-Silicon Photonics Foundry Process
Changes In The Management Board Of 3D-Micromac AG
TEL Introduces Episode UL As The Next Generation Etch Platform
Obducat Receives Order For Fully Automated Resist Processing Tool From A Customer In Asia
K-Space Offers A New Accessory For Their In Situ Metrology Tools
New Plant To Manufacture Graphene Electronics
EV Group Establishes State-of-the-art Customer Training Facility
South Korean Point Engineering Chooses ClassOne’s Solstice S8 For Advanced Semiconductor Plating

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