IBM reports that it has developed the first transistors using strained silicon directly on insulator (SSDOI) technology. The company says that the process provides high performance while eliminating manufacturing problems. IBM also claims to be the first to combine two different underlying silicon layers that simultaneously maximise the performance of the key transistors used in complementary metal oxide semiconductor (CMOS) devices. Both technologies aim at improved currents and removing the need for such rapid shrinkage of devices.

IBM reports that it has developed the first transistors using strained silicon directly on insulator (SSDOI) technology. The company says that the process provides high performance while eliminating manufacturing problems. IBM also claims to be the first to combine two different underlying silicon layers that simultaneously maximise the performance of the key transistors used in complementary metal oxide semiconductor (CMOS) devices. Both technologies aim at improved currents and removing the need for such rapid shrinkage of devices.

One big problem is current leakage through the substrate. Putting in the insulating layer blocks this current loss. Current strained silicon technology provides high electron mobility - and improved current performance - by stretching a silicon layer on top of an underlying silicon germanium (SiGe) layer. IBM has previously reported a 20-30% performance enhancement using this technology. However, the presence of a SiGe layer causes material and process integration challenges.

IBM's new approach is to fabricate transistors using ultra-thin SSDOI structures that bypass this SiGe layer providing high electron mobility while eliminating material and process integration problems.

To create SSDOI structured wafers a strained Si layer is first grown epitaxially on relaxed SiGe. The silicon stretches to match the SiGe lattice. The wafer carrying these layers is then bonded onto a wafer with an oxide layer. The strained silicon is thus bonded directly onto the oxide. A hydrogen implant is then used to weaken the SiGe layer. The bonded wafer is then cleaved through this weak plane in the composite wafer. The SiGe surface layer is then removed leaving just the strained silicon on top of the oxide.

Strain retention was confirmed in the strained Si layer after the layer transfer process and thermal cycles. Electron and hole mobility enhancements were confirmed in MOSFETs fabricated on the SSDOI wafers. Fabrication of sub-60nm FETs was also demonstrated on SSDOI.

The second development increases hole mobility, through the device channels. IBM has been able to integrate devices with 2.5 times higher hole mobility into conventional CMOS technology by combining two substrates in the same wafer. This results in a 40-65% performance enhancement.

CMOS is made of two types of transistors - positively-charged field effect transistors (PFETs), and negatively charged FETs (NFETs) - hence the “complementary” part of the name. Charges conduct better in some directions than others relative to the silicon lattice. By angling the lattice relative to the surface conduction layer of the silicon wafer one can get different performances. For PFETs, hole mobility is known to be 2.5 times higher on crystal surfaces where the silicon atoms are in the “(110)” surface-orientation. Unfortunately, normal silicon wafers are (100) surface-oriented, making for better NFETs.

IBM's hybrid-orientation technology (HOT) transfers a layer of the alternative surface-orientation silicon using a similar wafer bonding technique as in SSDOI. The layer is then patterned and a block-level trench etch carried out to expose the underlying bulk silicon orientation in some areas. Epitaxial regrowth brings the level of the exposed bulk silicon up to make a flat surface. Then CMOS processing on the hybrid substrate with different crystal orientations can achieve significant PFET performance enhancement. An enhancement of 40-65% for the PFET was demonstrated on a 90nm node CMOS technology.

"These two innovative techniques are relatively simple to implement using standard wafer processing techniques," says Dr TC Chen, science and technology vice-president at IBM Research. "Implementing either could provide the industry with higher performing and lower power chips - combining the techniques could generate even higher performance and lower power."

The company sees these technologies as possibly playing a role at the 45nm node. The International Technology Roadmap for Semiconductors (ITRS) puts this on the horizon around 2008, although this is not necessarily the time at which either technology would be introduced.

IBM plans to present details of the new techniques in two papers at the International Electron Devices Meeting (IEDM), December 7-10, 2003.

AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

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Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

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