Infineon Produces Process Test Chip
The chip enables tests of process sequences with a previously unsurpassed degree of precision and optimisation of functionality by performing measurements even during the manufacturing process. This allows faults to be detected more quickly, while boosting productivity and reducing production costs.
The development, production and practical deployment of the test chip were performed at Infineon's site in Regensburg. The test chip will initially be used in Infineon's Regensburg-based wafer production facility and later at other sites. The chip is based on a 0.35micron CMOS process and is produced on 200mm wafers. With its memory-like structure, the chip itself incorporates in excess of 1.2mn transistor functions on an area measuring only 6mm2.
The newly devised test chip is to be used to test vias, the conductive connections between two metallised layers. Since the typical failure probability for the vias in an advanced CMOS process is around 10 to 20ppb (parts per billion), a large quantity of test data is required in order to perform a statistical evaluation. For this purpose, the test chip features an array of 512x512 vias (262,144 in total), along with the associated selection transistors for the addressing function. On just one wafer, 60 imaging blocks with 42 test chips each have been mapped, which equates to 2500 test chips/wafer and as such around 640mn vias. Each via can be addressed individually, while its electrical resistance and voltage drop can be measured precisely.
The test chip concept is being further developed in co-operation with the Regensburg University of Applied Sciences so as to allow other process steps in the chip production sequence to be examined.
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