Analogue designers working with leading-edge processes need both good communications with the foundry and insight into semiconductor physics, writes Julian Hayes, VP of Marketing, Wolfson Microelectronics...

As new processes come on-line, foundries focus their initial efforts on digital applications leaving insufficient support for high-performance analogue applications, creating challenges for mixed-signal design teams. Overcoming these challenges requires more than good analogue design technique. As mixed-signal designs migrate to smaller, less mature process geometries design teams have little experience or data to work with.

Migration occurs for a number of reasons. The size of the design is one. Levels of integration practical with 0.18µm would become impossible with the more established processes, allowing larger, more complex designs. Designing in a leading-edge process also helps future-proof a design, ensuring that it can continue to be manufactured over a long product lifetime. The smaller geometry also provides greater performance and results in lower power for the digital portion of a design because it runs at a lower voltage.

The increased circuit density, higher speeds and lower voltages, that digital designers love, make the analogue designer's task much harder. More digital circuits at higher switching speeds generate much more noise. The lower operating voltage means that the analogue signals are smaller, so the noise has an even greater relative impact. Added to this is the reality that most of what foundries know about their leading-edge processes applies only to the digital design task. Analogue designers end up with more work and less support.

Analogue design tricks

Analogue designers must employ a variety of tricks to lower total noise to an acceptable level. Some are purely mechanical, some are circuit design techniques and some come from the process itself.

Some of the simplest tricks to employ are mechanical, not electrical. With proper circuit layout, for instance, the analogue sections of a design can be afforded a degree of isolation from noise. Keeping analogue sections in close proximity keeps signal leads short, minimising the chance of interfering signals coupling into the signal traces. Similarly, locating the highest-speed digital portions of the design well away from the analogue section reduces the noise energy density that reaches the analogue section.

Another mechanical trick is to improve the quality of the analogue ground reference by adding multiple connections from the chip ground to the circuit board. This involves increasing the number of bonding pads that connect to the chip's substrate and the number of bond wires that connect each pad to the lead frame. Either or both tricks may be useful, as they improve the ground reference in different ways.

When working with signals that have their origin off-chip, differences between the chip's ground reference and the external ground reference will show up as noise in the signal. A major source of this noise is the mass of high-speed current spikes the digital circuits put into the ground current. As this current leaves the chip, it passes through the bond wires, which have some inductance and resistance. The impedance these wires present to the current spikes causes a voltage drop, raising the chip's ground reference relative to external signals. Having multiple bond wires from a pad to the lead frame reduces the connection's inductance and resistance, lowering noise for external signals.

For internal signals, a similar effect occurs because of resistance in the substrate. Ground current flowing in the substrate causes an IR drop between ground reference points in the analogue circuit. The resulting ground voltage differences show up as noise in the on-chip analogue signals. The more pads connecting to the substrate, the more parallel paths exist for the current to flow through, reducing the IR drop between the analogue ground reference points on the chip.

Differential design helps

Circuit design techniques can also assist with this type of noise. Single-ended analogue circuits depend on the difference between the signal and a common ground reference. Differential circuits, however, provide two signals and depend on the difference between them rather than on an absolute ground reference. By making the analogue circuits differential in nature, designers can reduce the effect of on-chip ground noise.

There are also a number of semiconductor process techniques that designers can apply to reduce analogue noise. One straightforward approach is to increase the oxide thickness used in the analogue circuits. While this doesn't affect noise directly, it does provide a way of reducing the noise's impact.

As semiconductor lithography has become finer, so have the dimensions of all the component elements, including the oxide layer between the gate and the channel of MOS transistors. The thinner oxide layer is more susceptible to breakdown, which is one reason the operating voltage of transistors decreases in 0.18µm processes. By increasing the oxide thickness in the transistors used for the analogue circuits, designers can increase the operating voltage these transistors can tolerate. Operating the analogue circuits at a higher voltage than the digital section of a mixed-signal design improves the signal-to-noise ratio.

Deep-well isolation reduces noise

One of the more subtle process techniques designers can apply is to use deep-well isolation to reduce coupling of substrate noise. A typical CMOS transistor pair on a P-type substrate uses an N-well for the PMOS transistor while the NMOS transistor lies directly on the substrate (Figure 1).

Fig.1: A typical CMOS transistor pair on a P-type substrate uses an N-well for the PMOS transistor (left) while the NMOS transistor lies directly on the substrate (right)

Typically, to reduce interference from noisy digital blocks to sensitive analogue blocks, the positive supply connection to the N-wells in the noisy section will be routed independently to different pins than the corresponding connections to sensitive circuits. But since all the NMOS transistors share a common substrate, this trick cannot be used for the negative supply connected to the substrate. So there will be crosstalk of the supply rail voltage spikes caused by the digital circuitry into the supply rails of the analogue circuitry.
The deep-well isolation technique fabricates both transistor types in isolated wells (Figure 1). The PMOS transistor's N-well is extended and deepened to run underneath the NMOS, so that the NMOS transistor must use a P-well within the larger N-well to form the channel. With this fabrication technique, different NMOS transistors can have electrically isolated substrate connections. Therefore, it becomes feasible and worthwhile to route analogue and digital grounds back to separate pins, to minimise digital to analogue crosstalk.
To apply these techniques successfully, designers must be able to accurately model their designs and the noise sources. This is where working with leading-edge semiconductor processes becomes challenging for high-performance mixed-signal design. The models for leading edge-processes may be unrefined or even unavailable.

Models not always right

Some of the most important modelling elements for analogue designers are the transistor Spice models for a process. These models are essential to calculating the circuit's response to both signals and noise and to determining the usefulness of various noise reduction techniques. Without reasonably accurate models, designers cannot reliably produce a high-performance design. Unfortunately, process developers focus their initial efforts on the needs of the digital designer. Analogue designers, then, must develop close communications with the semiconductor foundry in order to get the information they will need.

The transistor Spice models for a 0.18µm process illustrate this point. Foundries routinely provide the models to their customers along with low-detail plots. Figure 2, comparing the model and measurements for a typical digital transistor, is typical of the data foundries routinely provide. It shows that digital designers have little to worry about. The models are more than adequate for digital designs, which typically are concerned with threshold voltages and switching times.

Fig.2: Comparison of the model and measurements for a typical digital transistor

Analogue designers, however, are interested in parameters such as signal gain, which the foundry may not provide. Therefore, the designers must request the raw data so they can create the plots they need.

One useful plot, for example, is the Early Voltage of a transistor, which measures small-signal gain. A typical result is shown in Figure 3, with both the model and actual measurements the foundry provided. The degree of agreement between the two is adequate for analogue designers, who use guard bands and error-compensating designs rather than models to ensure good design, but it does indicate the poor quality of early process models for analogue purposes.

Fig.3: One useful plot is the Early Voltage of a transistor, which measures small-signal gain. A typical result is shown with both the model and actual measurements the foundry provided

The situation can quickly become worse if the analogue designer doesn't want to use the standard digital transistor's design. Transistors for analogue design, for instance, often use a longer channel and a lower gate voltage in order to optimise analogue gain characteristics. Plugging these parameters into the Spice model results in the curves of Figure 4.

Fig.4: A Spice model simulation for analogue transistors with a longer channel and a lower gate voltage designed to optimise analogue gain characteristics

Here the difference can be as great as 50% - or a 3dB error in gain. While it might be possible to get the foundry to re-optimise the Spice parameters and produce a better fit, the analogue designer is usually stuck with the original digital model. With access to the foundry's measured data, at least, designers can interpret their simulations properly and assess their design's tolerance of the errors.

Missing models

Analogue designers must also deal with the probability that neither models nor data exist for some of the parameters they must consider in high-performance design. Wolfson ran into this problem in its design of a high-performance mixed-signal device at 0.18µm. The device combined a 100,000-gate DSP with a 14-bit analogue-to-digital converter to form the core of a digital radio for an automotive entertainment system. In order to achieve such high analogue precision in the presence of such a digital large noise generator, Wolfson needed to model the substrate currents in a deep-well isolated design.

Typical digital designs that use deep-well isolation have many N-well contacts as part of the logic design. Analogue designs, on the other hand, may have large regions where no N-well contacts exist. Such regions may be created by the presence of on-chip capacitors or by large NMOS output transistors. Without frequent N-well connections, the deep-well resistance between reference points becomes an important parameter to consider.

To determine deep-well resistance, the designers requested the doping profiles used in the construction of the deep-well transistors. From those profiles, illustrated in Figure 5, and knowledge of the doping-dependent carrier mobility, the designers could estimate both deep-well and isolated P-well sheet resistance.

Fig.5: Doping profiles used in the construction of deep-well transistors

Circumstances such as this demonstrate the need for analogue designers working with leading-edge processes to have both good communications with the foundry and their own insight into semiconductor physics. The many design tricks available for creating high-performance analogue design must be evaluated against the reality of the fabrication process. With older, established processes this evaluation follows proven well-understood methods and models. With emerging processes, however, designers must develop their own when aspiring to high-performance mixed-signal design.

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