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New Methods Of 3D Chip Integration (GmbH, Radfeld/Austria)

3D chip integration is a future-oriented option for optimising the cost of electronic systems. This new technology requires semiconductor manufacturing and packaging to be viewed as a whole. Producers of die bonding equipment have a key role in this process, writes Christoph Scheiring of Datacon Semiconductor Equipment...
When new technologies hit the headlines, typically the talk is about more gigahertz, fewer micrometers or higher integration densities. Sometimes it's about a company's claim to be the only legitimate representative of the innovation - and occasionally it's just to temporarily increase the company's share price.

In the background, a quieter revolution is taking place, one that cannot be baldly captured in slogans. Instead it causes more radical changes. We are talking about process technologies, manufacturing structures and new forms of collaboration between industry partners.

The reasons for this are the ever-increasing demand for modern semiconductor applications and continued extreme cost pressure. Conventional technologies cannot resolve these issues.

Innovative process technologies require closer collaboration between partners as the boundaries between semiconductor manufacture and assembly and packaging are becoming increasingly blurred. It is worth the IC manufacturer's while to communicate with their assembly partner at an early stage to ensure that they benefit from the most efficient system solutions offering the greatest reliability and performance results at the most competitive prices.

Trends and their limitations

The most important demands on microelectronics include more functionality at the chip level, smaller packages, shorter time-to-market and greater design security - and all of this at continually lower costs. SOCs (systems-on-chip) as a miniaturised and cost-effective response to the first challenge have brought great progress, but they quickly face limiting economic factors. This is especially true with embedded technologies for performance enhancement, where at least two different process technologies exist on the chip. An example would be the combination of high-density logic and broadband high-frequency circuits. Mixed technologies like this could be produced with improved performance at a lower cost by using different chip types suited for respective functions.

This is where the next challenge comes in that is sometimes known as "the wiring crisis". Connecting multi-pin chips at the board or substrate level leads to difficult routing and interference, especially with parallel data processing circuits and high-frequency applications. A solution can be found in the third dimension using stacks of chips. Here the boundaries between semiconductor manufacturing and packaging become blurred, requiring the integration of the assembly partner in the product and process definition.

Methods of 3D chip integration

The first stacked chips used components with peripheral connections adhesive-bonded and connected to each other at the edge with wire bonding. This is still a widely used method. A new approach developed by Infineon Technologies and Datacon Semiconductor Equipment bundles semiconductor production and packaging expertise as critical elements in a concerted effort to develop high-performance, low cost solutions. The new process allows a parallelisation of 3-dimensional (3D) chip integration. The work was carried out as part of a VSI project (Vertical System Integration) under the German federal government's Ministry of Education, Science, Research and Technology (BMBF). The two companies have completed development through to the production stage.

Expertise with surface-array pin patterns transferred to the inter-IC level was the starting point. Contact surfaces for the new process were copper squares measuring 10x10µm distributed over the chip surface in a 20µm grid. The copper squares were connected with a diffusion soldering procedure.

Innovative technology

The technology is called SOLID F2F, where SOLID stands for solid-liquid inter-diffusion, a bonding technology that uses a special soldering process. F2F stands for face-to-face, describing the orientation of two chips with their active sides facing each other.

Figure 1 shows the structure of a two-layer stack in SOLID F2F technology. The surface of the bottom chip is 5µm-thick copper. The top chip has a congruent structure of copper, which is also covered with a 3µm-thin layer of tin. The electrical connections are made through 10x10µm contact pads surrounded by 10µm-wide, non-metallised channels for electrical isolation. The rest of the surface is also metal-coated, forming an electrical barrier between the chips to be connected. The top and bottom chips are positioned congruently and soldered with the tin layer of the top chip. Conventional techniques are used to bond the external input and output connections. This SOLID bonding technology forms a contact interface that is only about 10µm thick with a contact density of more than 105/cm2. This guarantees excellent electrical performance.

This flat F2F metal connection is an inexpensive alternative to the increasing connection overhead for planar substrate or board connections. It offers higher signal integrity and less crosstalk, avoiding many problems common with high-frequency circuits.

Precise production equipment

Two Datacon systems represent the core technology for implementing the chip-stacking process. A high-precision flip-chip bonder (Figure 2) detaches the chips from wafer tape, flips them 180¡, optically aligns and then bonds them to a bottom wafer with a temporary fixing agent that holds the chips in position.

In the next process step the bottom wafer, completely covered with the top chips, is transferred as one unit to a specially developed chip-to-wafer bonder. Here it is hard-soldered in a forming gas atmosphere at 270¡C. The liquid tin reacts with the copper surfaces and is transformed into the high-melting-point alloy Cu-3Sn. This inter-metallic phase is thermodynamically stable, with a melting point of 600¡C, ensuring a temperature hierarchy with subsequent processes. In addition, the alloy retains exceptional electrical and thermal conductivity. The stacked chips are then detached and fed to a conventional assembly process.

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