Laser Thermal Process Ready For Market
LTP uses laser heating that can be focused at specific areas of the wafer (Figure 1), rather than across the wafer as happens in furnaces or with rapid thermal processing (RTP). Ultratech's platform brings together projection optics as used in lithography with the new annealing technology.
The challenge
The basic parts of semiconductor devices are the electrical switches called transistors. These are built up with regions of semiconductor material that can be switched from conducting to insulating behaviour. In a pure state, silicon is a pretty awful conductor of electricity but by adding "doping" impurities its conductivity can be boosted by many orders of magnitude. Some of these impurities - designated "donors" - have spare electrons that can easily be released into conduction. Others - called "acceptors" - grab electrons from the silicon leaving an oppositely charged "hole" that can be passed around between the atoms and hence conduct charge. Boron is commonly used as an acceptor and phosphorous as a donor.
These dopants are typically introduced at the wafer crystal growing phase to create the substrate and later selectively through ion implantation. One problem with ion implantation is that it produces damage to the crystal substrate. This damage kills the conductivity. Heating the wafer can repair the crystal structure, but then the dopant atoms tend to diffuse away from where they were implanted. This smears the doping pattern needed to create transistors, reducing performance. This heating process is called annealing. Fast heating can reduce the amount of diffusion and rapid thermal processing technologies have displaced slower batch furnace processes since the mid-1990s.
A typical RTP step raises the wafer temperature to 1000-1100¡C for 1sec. However, significant dopant diffusion still takes place. Improved RTP would need annealing temperatures of 1300-1350¡C for even shorter time frames of the order of milliseconds. This raises the distinct possibility that the technique will not be much use beyond the 90nm technology node.
For each successive device generation, from 90nm through 20nm, requirements continue to tighten - sheet resistance must be effectively lower and junction depth increasingly shallow, with more abrupt and much higher activation of dopants needed to achieve the lower sheet resistance. Shallow junctions are particularly important for moving to higher performance, smaller devices.
Solution?
Laser spike annealing (LSA) is Ultratech's proposed solution to the annealing problem. This operates at near-instantaneous timeframes (10-200µsec), at temperatures up to 1350(C - just below silicon's melting point. Simulations suggest that a much improved dopant profile would result over RTP (Figure 2). The plot indicates that a much shallower abrupt junction with higher boron concentrations could be achieved as a result of the nominal diffusion that occurs for such fast heating. High boron concentration translates into higher conductivity - sheet resistances as low as 100½/square could be achievable.
Ultratech's LSA combines a continuous-wave (CW) laser with projection optics, aiming at ultra-shallow junction formation down to at least the 45nm node (Figure 1). The wafer is scanned under the stationary, shaped laser beam, mounted on an X-Y linear stage. A constant peak temperature is maintained by feeding back a pyrometer signal to a laser power attenuator. The process could enable highly uniform activation in the solid-phase state thus eliminating the need for any additional process steps.
The heating and cooling of the wafer surface occurs within milliseconds. With such time-scales, processes that can degrade device performance - such as boron penetration through oxide layers or transient enhanced diffusion - are suppressed. Ultratech has not observed any such degrading processes in its work, allowing it to claim a "near zero" thermal budget for the process. Since only the surface layer is heated (Figure 3), the bulk of the substrate does not rise to temperatures of more than 50¡C. In RTP, the substrate can reach 900-1050¡C.
A variable size laser-beam spot can be used to heat up localised areas on the wafer, as well as on individual die, without affecting the surrounding areas. This "spot annealing" enables a degree of precision unachievable with previous technologies.
Figure 4 compares sheet resistance and junction depth for alternative thermal processing methods - conventional RTP, laser spike annealing (LSA), laser and flash annealing. The graph is a compilation of various data points available in the public domain, including the ITRS, as well as Ultratech's own internal data.
Laser annealing (LTP) goes beyond LSA by melting and then recrystallising the damaged material. Longer term, this technique could lead to even better sheet resistances. However, at the current stage of development there are a number of issues with integrating this technique into current semiconductor production processes. Therefore, Ultratech is promoting LSA as a "plug compatible" direct replacement for RTP. To use LSA, a fab would merely have to make the usual adjustments needed to bring a new tool into a process. According to Ultratech's director for laser product technology, Lucia Feng, LSA would give definite advantages in 65nm processes, while a transition to the more advanced LTP laser anneal technology may be needed for 45nm or perhaps lower roadmap nodes.
LSA shows advantage even compared with the modified "flash anneal" RTP process where an extra bank of heating lamps is brought on for a very short time to provide a heating spike.
Figure 5 illustrates how a proprietary Ultratech technology minimises temperature variations across the wafer. This is measured by the amount of reflected light on a 12x15mm test die containing various circuit component types. Reflection is an indication of unabsorbed light - heating depends upon absorption. For these measurements, an 80µm-diameter laser spot (corresponding to the thermal averaging distance) was scanned across the die while monitoring the reflected power. In a traditional laser-annealing approach, numerous peaks and valleys are seen, representing large temperature variations. Ultratech's hardware optimisation method shows a much quieter topography.
The traditional map shows variations of the order of 20%. With the hardware optimisation, reflectance variation is reduced to less than 2%, enabling a minimal amount of temperature variation on the wafer. The Ultratech technique uses both the wavelength of the excimer laser light and other proprietary techniques to achieve this result. With the halogen lamps used in RTP, a broadband of wavelengths is produced, which are absorbed differently by the thin film structures that result from memory or logic processing.
The long march
Early experiments in laser annealing in the mid-1980s used yttrium aluminium garnet (YAG) lasers. One of the biggest roadblocks was to create a uniform laser beam in a consistent and fast manner. Uniform illumination was of the order of millimetres rather than the centimetres required. Pulse-to-pulse repeatability was at a poor 10% level. Later work with excimer lasers improved pulse-to-pulse uniformity to 5%, still not adequate for commercial use.
While straight productivity measures suggest that LSA has 50-75% the throughput of RTP, Ultratech's model suggests comparable cost of ownerships when factors such as consumables are included. For example, halogen lamps need frequent replacement while excimer lasers have a ten year lifespan. Further, Ultratech is naturally working to improve productivity to tip the balance in LSA's favour.
Ultratech has worked in close co-operation with several of the industry's leading chipmakers in both the USA and Japan to validate the technology. Ultratech reports that LTP technology has demonstrated the ability to activate extremely shallow junctions and contacts in just nanoseconds, thereby achieving the desired performance characteristics while using zero thermal budget.
In terms of transistor performance, 5-10% improvements in on/off currents and switching speeds are suggested by preliminary data. Test results demonstrate abrupt profile junctions with high surface concentrations down to the 20nm node. Tests also indicate that the process results are relatively insensitive to device and wafer pattern densities. Ultratech has already been awarded more than 20 patents with 40 more pending on the technology.
Somit Talwar, Ultratech vice-president for laser technology, reports: "Since the use of lasers for the annealing process had long been attempted, but without sufficient success, a new approach was needed. We believe that we have amassed the world's foremost team of experts in the emerging laser processing arena and paired them with Ultratech's projection lithography experts to tackle this challenge."
Ultratech came to the conclusion that it had resolved all of the known technical issues in 2002. Two alpha R&D tools were shipped and a booking has been made on a pre-production tool. The first production tools are due to ship at the end of this year. Volume production shipments are expected to start in 2004.
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