News Article
Toshiba licenses IMEC’s technology
The company licenses power efficient, flexible processor technology developed by the independent European research centre.
IMEC, Europe’s independent nanoelectronics research institute announced that Toshiba,
an integrated device manufacturer, has licensed IMEC technology for designing power efficient, flexible processors in a single and multiprocessor architecture. The agreement concerns IMEC’s ADRES reconfigurable processor template, the DRESC compiler, and the MPSoC (multi processor system on chip) suite of design tools. Toshiba will also co-operate with IMEC to develop processors and tools that enable gigabit/s demodulation.
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a processor architecture designed for wireless and multimedia processing in single and multiprocessor systems. ADRES processors are suited for future mobile terminals, such as software defined radios. They combine state of the art power efficiency, excellent performance, and flexibility.
Through an XML template, designers can create the ADRES processor instance that is best suited for their applications. And applications for an ADRES processor can be completely programmed in a high level programming language (C) and compiled with the DRESC compiler, included in the license. This is of key importance for short time to market.
MPSoC is a suite of tools to help build and map applications for multiprocessor platforms. The suite’s first tool set, called CleanC, allows designers to write sequential, high level code that is optimised for parallelisation. The second tool set then enables mapping the sequential C code on a multiprocessor platform. MPSoC relieves the designers of having to code synchronisation, data communication between threads, and memory organisation. Thanks to the parallelisation tools, for instance, several multi-threaded versions of the same application can be explored in a short time. This greatly reduces the application complexity and design time, enabling designers to bring multiprocessor based embedded system platforms faster to the market.
“Before entering into this agreement, Toshiba thoroughly evaluated the IMEC technology. It then decided not only to license ADRES and MPSoC, but also to co-operate with IMEC to develop processors and tools that enable gigabit/s demodulation. This testifies that IMEC’s research into efficient embedded multiprocessor systems is world class”, said Rudy Lauwereins, Vice President Nomadic Embedded Systems at IMEC.
“We are confident that IMEC’s dynamic reconfigurable processor technology will bring significant advantage to the development of our wireless baseband SoCs in terms of design time, flexibility and area;” said Tohru Furuyama, General Manager of Centre for Semiconductor Research & Development at Toshiba. “We are looking forward to collaborating with IMEC which will allow us to leverage on the expertise and knowledge of IMEC’s research team and enable us to also provide valuable technologies and products to our customers.”
an integrated device manufacturer, has licensed IMEC technology for designing power efficient, flexible processors in a single and multiprocessor architecture. The agreement concerns IMEC’s ADRES reconfigurable processor template, the DRESC compiler, and the MPSoC (multi processor system on chip) suite of design tools. Toshiba will also co-operate with IMEC to develop processors and tools that enable gigabit/s demodulation.
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a processor architecture designed for wireless and multimedia processing in single and multiprocessor systems. ADRES processors are suited for future mobile terminals, such as software defined radios. They combine state of the art power efficiency, excellent performance, and flexibility.
Through an XML template, designers can create the ADRES processor instance that is best suited for their applications. And applications for an ADRES processor can be completely programmed in a high level programming language (C) and compiled with the DRESC compiler, included in the license. This is of key importance for short time to market.
MPSoC is a suite of tools to help build and map applications for multiprocessor platforms. The suite’s first tool set, called CleanC, allows designers to write sequential, high level code that is optimised for parallelisation. The second tool set then enables mapping the sequential C code on a multiprocessor platform. MPSoC relieves the designers of having to code synchronisation, data communication between threads, and memory organisation. Thanks to the parallelisation tools, for instance, several multi-threaded versions of the same application can be explored in a short time. This greatly reduces the application complexity and design time, enabling designers to bring multiprocessor based embedded system platforms faster to the market.
“Before entering into this agreement, Toshiba thoroughly evaluated the IMEC technology. It then decided not only to license ADRES and MPSoC, but also to co-operate with IMEC to develop processors and tools that enable gigabit/s demodulation. This testifies that IMEC’s research into efficient embedded multiprocessor systems is world class”, said Rudy Lauwereins, Vice President Nomadic Embedded Systems at IMEC.
“We are confident that IMEC’s dynamic reconfigurable processor technology will bring significant advantage to the development of our wireless baseband SoCs in terms of design time, flexibility and area;” said Tohru Furuyama, General Manager of Centre for Semiconductor Research & Development at Toshiba. “We are looking forward to collaborating with IMEC which will allow us to leverage on the expertise and knowledge of IMEC’s research team and enable us to also provide valuable technologies and products to our customers.”
