News Article
TSMC ramps 40nm process technology to volume production
The foundry’s first 40 nanometre (nm) process lowers costs and power for high performance and wireless devices to innovate out of the downturn.
TSMC has announced volume production of the foundry segment’s only 40nm semiconductor manufacturing process with the successful ramp of its 40nm General Purpose (G) and Low Power (LP) versions. A comprehensive design infrastructure including library, IP, design flow, engineering service, and monthly CyberShuttle prototyping vehicles is also ready for these two processes.
The 40nm process is one of the semiconductor industry’s most advanced manufacturing process technology. TSMC’s 40nm G and LP processes were formally announced in March as part of the company’s advanced technology offering. The 40G process targets performance driven applications including CPU, GPU (graphic processing units), game consoles, networking, FPGA, hard disc drive, and other devices. The 40LP process targets low power applications including cellular baseband, application processors, portable consumer and wireless connectivity devices.
"We view 40nm as an important process node for the cost effective development of graphics chips and other devices, especially in 2009. This is another example of a long and successful history of AMD and TSMC ramping leading edge processes," said Rick Bergman, senior vice president & general manager, AMD Graphics Products Group.
“Today designers are faced with the challenge of increasing the functionality of their product while not increasing power consumption. By rolling out the industry’s most advanced programmable logic devices at 40nm, we are enabling designers to quickly achieve new levels of integration and innovation, while staying within their power budgets,” said Bill Hata, Altera senior vice president of worldwide operations and engineering.
"High performance GPUs are only continuing to grow in importance for a variety of industries," said Debora Shoquist, NVIDIA senior vice president of operations. "The advantages that TSMC's 40nm G process provides to designing a GPU will allow us to continue pushing the limits of what’s currently possible.”
“While timed to respond to the technical requirements of our broad customer base, the two processes are clearly the right manufacturing processes at the right time and can help the semiconductor industry, and conceivably other portions of the global economy, to innovate out of the current downturn,” said Jason Chen, vice president, worldwide sales & marketing, TSMC.
TSMC’s 40G and 40LP processes passed process qualification, reaching “first wafers out” status as planned, and completed product qualification in October when first customer wafers entered production. As with every TSMC process node, the 40G and 40LP processes offer a full range of mixed signal and RF options, along with embedded memory, to support a broad range of analogue/RF intensive and memory rich applications.
“Once again we have continued TSMC’s long standing record of delivering commercially available processes exactly when we said we would and way ahead of competitors,” said Dr. Mark Liu, senior vice president, advanced technology business, TSMC.
Multiple customers at 40nm have adopted Reference Flow 9.0, a production proven design infrastructure that allows designers to take full advantage of 40G and 40LP processes. TSMC’s Reference Flow includes a number of innovative power reduction techniques and tools that allow designers considering 45nm design rules to transparently target their designs to 40nm processes without explicitly dealing with a multitude of scaling factors. Reference Flow also facilitates enhanced timing, statistical design and design for manufacturing (DFM).
TSMC's 40G and 40LP processes offer designers up to a 2.35 times raw gate density improvement over the 65nm node. The 40G process is up to 30% faster than TSMC’s 65nm GP process at the same leakage, or up to 70% lower leakage at the same speed. In addition, it provides up to 45% lower active power than the 65GP process. The 40LP process provides up to 46% lower leakage and up to 50% lower active power than TSMC’s 65LP at the same speed. It also features the smallest SRAM cell size, 0.242μm2, and macro size in production today.
The 40nm process is one of the semiconductor industry’s most advanced manufacturing process technology. TSMC’s 40nm G and LP processes were formally announced in March as part of the company’s advanced technology offering. The 40G process targets performance driven applications including CPU, GPU (graphic processing units), game consoles, networking, FPGA, hard disc drive, and other devices. The 40LP process targets low power applications including cellular baseband, application processors, portable consumer and wireless connectivity devices.
"We view 40nm as an important process node for the cost effective development of graphics chips and other devices, especially in 2009. This is another example of a long and successful history of AMD and TSMC ramping leading edge processes," said Rick Bergman, senior vice president & general manager, AMD Graphics Products Group.
“Today designers are faced with the challenge of increasing the functionality of their product while not increasing power consumption. By rolling out the industry’s most advanced programmable logic devices at 40nm, we are enabling designers to quickly achieve new levels of integration and innovation, while staying within their power budgets,” said Bill Hata, Altera senior vice president of worldwide operations and engineering.
"High performance GPUs are only continuing to grow in importance for a variety of industries," said Debora Shoquist, NVIDIA senior vice president of operations. "The advantages that TSMC's 40nm G process provides to designing a GPU will allow us to continue pushing the limits of what’s currently possible.”
“While timed to respond to the technical requirements of our broad customer base, the two processes are clearly the right manufacturing processes at the right time and can help the semiconductor industry, and conceivably other portions of the global economy, to innovate out of the current downturn,” said Jason Chen, vice president, worldwide sales & marketing, TSMC.
TSMC’s 40G and 40LP processes passed process qualification, reaching “first wafers out” status as planned, and completed product qualification in October when first customer wafers entered production. As with every TSMC process node, the 40G and 40LP processes offer a full range of mixed signal and RF options, along with embedded memory, to support a broad range of analogue/RF intensive and memory rich applications.
“Once again we have continued TSMC’s long standing record of delivering commercially available processes exactly when we said we would and way ahead of competitors,” said Dr. Mark Liu, senior vice president, advanced technology business, TSMC.
Multiple customers at 40nm have adopted Reference Flow 9.0, a production proven design infrastructure that allows designers to take full advantage of 40G and 40LP processes. TSMC’s Reference Flow includes a number of innovative power reduction techniques and tools that allow designers considering 45nm design rules to transparently target their designs to 40nm processes without explicitly dealing with a multitude of scaling factors. Reference Flow also facilitates enhanced timing, statistical design and design for manufacturing (DFM).
TSMC's 40G and 40LP processes offer designers up to a 2.35 times raw gate density improvement over the 65nm node. The 40G process is up to 30% faster than TSMC’s 65nm GP process at the same leakage, or up to 70% lower leakage at the same speed. In addition, it provides up to 45% lower active power than the 65GP process. The 40LP process provides up to 46% lower leakage and up to 50% lower active power than TSMC’s 65LP at the same speed. It also features the smallest SRAM cell size, 0.242μm2, and macro size in production today.
